diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | src/Top.bs | 16 | ||||
| -rw-r--r-- | src/Uart.bs | 76 |
3 files changed, 41 insertions, 53 deletions
@@ -17,7 +17,7 @@ flash: tmp/$(TOPMODULE).bin .PHONY: all clean flash tmp/%.bin: tmp/%.asc - icetime -d up5k -c 12 $< + # icetime -d up5k -c 12 $< icepack $< $@ tmp/%.asc: tmp/%.json src/icebreaker.pcf nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \ @@ -34,9 +34,7 @@ mkTop = bitState :: Reg (Bit 1) <- mkReg 0 uart <- mkUart (clockFreqHz / 9600) - btn1State :: Reg (Bit 1) <- mkReg 0 - {- lastByte :: Reg (Bit 8) <- mkReg 0x21 tick <- mkDivider (clockFreqHz) rules @@ -45,13 +43,6 @@ mkTop = "recv": when tick.clk ==> do byte <- uart.recv.get lastByte := byte - -} - rules - -- "echo": when True ==> do - -- byte <- uart.recv.get - -- uart.send.put byte - "say_one": when btn1State /= 0 ==> do - uart.send.put 0x31 interface Top -- RS232 @@ -60,8 +51,8 @@ mkTop = uart.rxPin bit tx = uart.txPin -- Onboard LEDs - ledR_N = 1 - ledG_N = uart.debugBit + ledR_N = uart.txPin + ledG_N = uart.txPin -- RGB LED driver ledRed_N = 1 ledGrn_N = 1 @@ -72,8 +63,7 @@ mkTop = led3 = 0 led4 = 0 led5 = 0 - btn1 bit = do - btn1State := bit + btn1 _ = return () btn2 _ = return () btn3 _ = return () {-# verilog mkTop #-} diff --git a/src/Uart.bs b/src/Uart.bs index 182236d..2cfe14a 100644 --- a/src/Uart.bs +++ b/src/Uart.bs @@ -50,26 +50,29 @@ mkTxUart baudClock bufferSize = module fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize state :: Reg TxState <- mkReg Idle + pin :: Reg (Bit 1) <- mkReg 1 + rules - "uart_tx_update_state": when baudClock.clk ==> do - case state of - Idle -> do + "uart_tx": when baudClock.clk + rules + "uart_tx_idle": when Idle <- state ==> do + pin := 1 b <- (toGet fifo).get state := Start b - Start b -> do + "uart_tx_start": when Start b <- state ==> do + pin := 0 state := Data b 7 - Data _ 0 -> do - state := Stop - Data b n -> do - state := Data (b >> 1) (n - 1) - Stop -> do + "uart_tx_data": when Data b n <- state ==> do + pin := b[0:0] + if n == 0 then + state := Stop + else + state := Data (b >> 1) (n - 1) + "uart_tx_stop": when Stop <- state ==> do + pin := 1 state := Idle interface TxUart - pin = case state of - Idle -> 1 - Start _ -> 0 - Data b _ -> b[0:0] - Stop -> 1 + pin = pin send = toPut fifo -- | The state of the RX side of the UART. @@ -96,36 +99,31 @@ interface RxUart = mkRxUart :: Clock -> Integer -> Module RxUart mkRxUart baudClock bufferSize = module - fifo :: FIFOF (Bit 8) <- mkUGSizedFIFOF bufferSize + fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize state :: Reg RxState <- mkReg Idle + pin :: Wire (Bit 1) <- mkWire debugBit :: Reg (Bit 1) <- mkReg 1 - interface RxUart - pin bit = when_ baudClock.clk $ do - nextState :: RxState <- case state of - Idle -> do - debugBit := bit - if bit == 0 then - return (Data 0 0) + + rules + "uart_rx": when baudClock.clk + rules + "uart_rx_idle": when Idle <- state ==> + if pin == 0 then + state := Data 0 0 else - return Idle - Data hi n -> do - debugBit := bit - -- // Timing estimate: 1000010.53 ns (0.00 MHz) - -- let b :: Bit 8 = bit ++ hi[7:1] - let b :: Bit 8 = hi[7:1] ++ bit + state := Idle + "uart_rx_data": when Data hi n <- state ==> do + debugBit := pin + let b :: Bit 8 = hi[7:1] ++ pin if n == 7 then do - when_ fifo.notFull $ do - fifo.enq b - return Idle + fifo.enq b + state := Idle else - return (Data b (n + 1)) - state := nextState - recv = interface Get - get = do - let byte = fifo.first - fifo.deq - return byte - when fifo.notEmpty + state := Data b (n + 1) + + interface RxUart + pin bit = pin := bit + recv = toGet fifo debugBit = debugBit -- | An 8n1 UART. |