diff options
Diffstat (limited to 'fpga/Makefile')
| -rw-r--r-- | fpga/Makefile | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/fpga/Makefile b/fpga/Makefile index edbb7d1..24e8ace 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -1,6 +1,6 @@ BSC_COMP_FLAGS = -bdir tmp -p src:+ -simdir tmp -vdir tmp BSC_LINK_FLAGS = -bdir tmp -simdir tmp -vdir tmp -BSC_SOURCES = BRAM2.v FIFO1.v FIFO10.v RevertReg.v SizedFIFO.v +BSC_SOURCES = BRAM2.v FIFO1.v FIFO10.v RevertReg.v SizedFIFO.v TriState.v all: tmp/mkTop.bin flash: tmp/mkTop.bin @@ -15,8 +15,11 @@ tmp/%.asc tmp/%-report.json: tmp/%.json src/icebreaker.pcf nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \ --asc $@ --report tmp/$*-report.json \ --pcf src/icebreaker.pcf --json $< -tmp/mkTop.json: tmp/mkTop.v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES)) +tmp/mkTop.json: tmp/mkTop.rewritten.v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES)) yosys -ql tmp/mkTop.yslog -p 'synth_ice40 -top mkTop -json $@' $^ +tmp/mkTop.rewritten.v: tmp/mkTop.v + cp $< $@ + perl $(BSC_SRC)/util/scripts/basicinout.pl $@ tmp/mkTop.v: @mkdir -p $(dir $@) bsc -u -verilog -g mkTop $(BSC_COMP_FLAGS) src/Top.bs |