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-rw-r--r--fpga/src/Clock.bs19
1 files changed, 0 insertions, 19 deletions
diff --git a/fpga/src/Clock.bs b/fpga/src/Clock.bs
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--- a/fpga/src/Clock.bs
+++ /dev/null
@@ -1,19 +0,0 @@
--- | A simple clock package.
-package Clock where
-
-interface Clock =
- clk :: Bool
-
--- TODO: Make a multiclock that uses one count for all the sub-clocks in the
--- design.
-
-mkClock :: Bit n -> Module Clock
-mkClock divisor =
- module
- count :: Reg (Bit n) <- mkReg 0
- rules
- when True ==> count := if count == divisor - 1 then 0 else count + 1
- interface Clock
- clk = count == 0
-
--- vim: set ft=haskell :