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-rw-r--r--src/UART.bs101
1 files changed, 0 insertions, 101 deletions
diff --git a/src/UART.bs b/src/UART.bs
deleted file mode 100644
index f837949..0000000
--- a/src/UART.bs
+++ /dev/null
@@ -1,101 +0,0 @@
-package UART where
-
-import GetPut
-import Util
-
-interface Clock =
- clk :: Bool
-
-defaultClock :: Clock
-defaultClock =
- interface Clock
- clk = True
-
-mkDivider :: Integer -> Clock -> Module Clock
-mkDivider divisor clockIn =
- module
- count <- mkReg 0
-
- rules
- "increment_divider": when clockIn.clk ==> do
- if count == fromInteger divisor then do
- count := 0
- else
- count := count + 1
-
- interface Clock
- clk = count == 0
-
-interface ShiftRegister =
- get :: Get (Bit 1)
- put :: Put (Bit 1)
-
-mkShiftRegister :: Module ShiftRegister
-mkShiftRegister =
- module
- reg :: Reg (Bit 8) <- mkReg 0
-
- interface ShiftRegister
- get = interface Get
- get = return 0
- put = interface Put
- put bit = do
- return ()
-
--- An 8n1 UART.
-interface UART =
- -- The RX pin.
- rxPin :: Bit 1 -> Action
- -- The TX pin.
- txPin :: Bit 1
-
- -- Reads a byte from the UART.
- rxByte :: Get (Bit 8)
- -- Writes a byte to the UART.
- txByte :: Put (Bit 8)
-
-mkUART :: Integer -> Module UART
-mkUART baudDivisor =
- module
- baud <- mkDivider baudDivisor defaultClock
-
- count :: Reg (Bit 4) <- mkReg 0
- rules
- "increment_count": when baud.clk ==> do
- count := count + 1
-
- let start = 0
- d0 = 1
- d1 = 0
- d2 = 0
- d3 = 0
- d4 = 1
- d5 = 0
- d6 = 0
- d7 = 0
- stop = 1
-
- interface UART
- rxPin _bit = when_ baud.clk $ do
- return () -- TODO
- txPin = case count of
- 0 -> start
- 1 -> d0
- 2 -> d1
- 3 -> d2
- 4 -> d3
- 5 -> d4
- 6 -> d5
- 7 -> d6
- 8 -> d7
- 9 -> stop
- _ -> 1
-
- rxByte = interface Get
- get = return 0 when False
- txByte = interface Put
- put _ = do
- -- TODO
- return ()
-
--- vim: set ft=haskell :