diff options
Diffstat (limited to 'src/Uart.bs')
| -rw-r--r-- | src/Uart.bs | 39 |
1 files changed, 17 insertions, 22 deletions
diff --git a/src/Uart.bs b/src/Uart.bs index d79f246..47d32e0 100644 --- a/src/Uart.bs +++ b/src/Uart.bs @@ -75,8 +75,8 @@ mkTxUart baudClock bufferSize = -- | The state of the RX side of the UART. data RxState - = -- | The UART is not currently receiving anything. May transition to - -- 'Data 0 0' when the start bit is received. + = -- | The initial state of the UART, and the state after receiving the stop + -- bit. May transition to 'Data 0 0' when the start bit is received. Idle | -- | In the 'Data _ n' state, the UART has received the start bit and 'n' -- data bits, and is about to receive more data bits. 'Data _ n' @@ -96,7 +96,7 @@ interface RxUart = -- | Reads a byte from the UART's receive buffer. recv :: Get (Bit 8) - debugBit :: Bit 1 + debugPin :: Bit 1 mkRxUart :: Clock -> Integer -> Module RxUart mkRxUart baudClock bufferSize = @@ -104,32 +104,26 @@ mkRxUart baudClock bufferSize = fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize state :: Reg RxState <- mkReg Idle pin :: Wire (Bit 1) <- mkWire - debugBit :: Reg (Bit 1) <- mkReg 1 + debugPin :: Wire (Bit 1) <- mkWire rules "uart_rx": when baudClock.clk rules - "uart_rx_idle": when Idle <- state ==> - if pin == 0 then do - debugBit := pin - state := Data 0 0 - else - state := Idle - "uart_rx_data": when Data oldBits n <- state ==> do - let newBits = pin ++ oldBits[6:0] - if n == 7 then do - fifo.enq newBits - state := Stop - else - state := Data newBits (n + 1) - "uart_rx_stop": when Stop <- state ==> do - debugBit := pin + "uart_rx_idle_to_start": when Idle <- state, pin == 0 ==> do + state := Data 0 0 + "uart_rx_data_to_data": when Data bits n <- state, n < 7 ==> do + state := Data (bits[6:0] ++ pin) (n + 1) + "uart_rx_data_to_stop": when Data bits 7 <- state ==> do + fifo.enq (bits[6:0] ++ pin) + state := Stop + "uart_rx_stop": when Stop <- state, pin == 1 ==> do state := Idle + "debugPin": when True ==> debugPin := if fifo.notEmpty then 1 else 0 interface RxUart pin bit = pin := bit recv = toGet fifo - debugBit = debugBit + debugPin = debugPin -- | An 8n1 UART. interface Uart = @@ -142,7 +136,8 @@ interface Uart = recv :: Get (Bit 8) -- | Writes a byte to the UART's transmit buffer. send :: Put (Bit 8) - debugBit :: Bit 1 + + debugPin :: Bit 1 mkUart :: Integer -> Module Uart mkUart baudDivisor = @@ -156,6 +151,6 @@ mkUart baudDivisor = txPin = tx.pin recv = rx.recv send = tx.send - debugBit = rx.debugBit + debugPin = rx.debugPin -- vim: set ft=haskell : |