diff options
Diffstat (limited to 'src/Uart.bs')
| -rw-r--r-- | src/Uart.bs | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/src/Uart.bs b/src/Uart.bs index 47d32e0..1059a65 100644 --- a/src/Uart.bs +++ b/src/Uart.bs @@ -86,8 +86,8 @@ data RxState | -- | In the 'Stop' state, the UART has received the start and data bits, -- and is waiting for the stop bit (which is ignored). Transitions to -- 'Idle'. - Stop - deriving (Bits) + Stop (Bit 8) + deriving (Bits, FShow) -- | The RX side of the UART. interface RxUart = @@ -96,15 +96,12 @@ interface RxUart = -- | Reads a byte from the UART's receive buffer. recv :: Get (Bit 8) - debugPin :: Bit 1 - mkRxUart :: Clock -> Integer -> Module RxUart mkRxUart baudClock bufferSize = module fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize state :: Reg RxState <- mkReg Idle pin :: Wire (Bit 1) <- mkWire - debugPin :: Wire (Bit 1) <- mkWire rules "uart_rx": when baudClock.clk @@ -112,18 +109,16 @@ mkRxUart baudClock bufferSize = "uart_rx_idle_to_start": when Idle <- state, pin == 0 ==> do state := Data 0 0 "uart_rx_data_to_data": when Data bits n <- state, n < 7 ==> do - state := Data (bits[6:0] ++ pin) (n + 1) + state := Data (pin ++ bits[7:1]) (n + 1) "uart_rx_data_to_stop": when Data bits 7 <- state ==> do - fifo.enq (bits[6:0] ++ pin) - state := Stop - "uart_rx_stop": when Stop <- state, pin == 1 ==> do + state := Stop (pin ++ bits[7:1]) + "uart_rx_stop_to_idle": when Stop bits <- state, pin == 1 ==> do + fifo.enq bits state := Idle - "debugPin": when True ==> debugPin := if fifo.notEmpty then 1 else 0 interface RxUart pin bit = pin := bit recv = toGet fifo - debugPin = debugPin -- | An 8n1 UART. interface Uart = @@ -137,8 +132,6 @@ interface Uart = -- | Writes a byte to the UART's transmit buffer. send :: Put (Bit 8) - debugPin :: Bit 1 - mkUart :: Integer -> Module Uart mkUart baudDivisor = module @@ -151,6 +144,5 @@ mkUart baudDivisor = txPin = tx.pin recv = rx.recv send = tx.send - debugPin = rx.debugPin -- vim: set ft=haskell : |