| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-10-23 | checkpoint; something is broken with timing | Nathan Ringo | |
| 2024-10-20 | Maybe repaired UART, I2C, and HyperBus (but now getting a weird error)... | Nathan Ringo | |
| 2024-10-08 | Preparation to start using separate clock domains. | Nathan Ringo | |
| 2024-10-08 | Reorganization and rewiring. | Nathan Ringo | |
| 2024-10-08 | Split the simulator back out to its own package. | Nathan Ringo | |
| This ensures that the presence of Inouts doesn't make Bluesim mad. | |||
| 2024-10-02 | Adds tristates for HyperBus. | Nathan Ringo | |
| This might need to be remodularized; Bluesim doesn't support Inouts, so this fails to build there for now. It probably makes sense to split out the board to its own package, then go back to having Top and TopSim packages, where only Top wires it up to Tristates. | |||
| 2024-09-24 | Fix echo. | Nathan Ringo | |
| 2024-09-24 | Another reorg. | Nathan Ringo | |
| 2024-09-23 | Adds README, moves fpga stuff to a subdirectory. | Nathan Ringo | |
 |
index : numini | |
| A toy CPU. | Nathan Ringo |
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