From d202daead0f05ecb60580fa7be2f23df8c4542fc Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Wed, 18 Sep 2024 14:09:34 -0500
Subject: Fix the UART TX.

---
 Makefile      |  3 ++-
 src/TopSim.bs |  9 ++++++++-
 src/Uart.bs   | 14 ++++++--------
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/Makefile b/Makefile
index 6b5bd2b..a7752ba 100644
--- a/Makefile
+++ b/Makefile
@@ -14,7 +14,7 @@ clean:
 flash: tmp/$(TOPMODULE).bin
 	sudo iceprog $<
 gtkwave: tmp/sim.vcd
-	gtkwave $<
+	gtkwave -A $<
 .PHONY: all clean flash gtkwave
 
 tmp/sim.vcd: tmp/$(TOPMODULE)Sim.exe
@@ -35,6 +35,7 @@ tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo
 tmp/%.bo:
 	@mkdir -p $(dir $@)
 	bsc -verilog $(BSC_COMP_FLAGS) $<
+.PHONY: tmp/$(TOPFILE).bo
 
 tmp/depends.mk:
 	@mkdir -p $(dir $@)
diff --git a/src/TopSim.bs b/src/TopSim.bs
index 5ba7232..93fef14 100644
--- a/src/TopSim.bs
+++ b/src/TopSim.bs
@@ -1,16 +1,23 @@
 package TopSim where
 
+import GetPut
 import Top
+import Uart
 
 mkTopSim :: Module Empty
 mkTopSim =
   module
     timer :: Reg (Bit 8) <- mkReg 0
 
+    uart <- mkUart 1
+
     rules
       when True ==> do
         timer := timer + 1
-      when (timer == 0xff) ==> do
+      when (timer == 0x00) ==> uart.send.put 0x81
+      when (timer == 0x01) ==> uart.send.put 0x18
+      when (timer == 0x02) ==> uart.send.put 0x81
+      when (timer == 0x40) ==> do
         $finish
 
 -- vim: set ft=haskell :
diff --git a/src/Uart.bs b/src/Uart.bs
index f66970c..d79f246 100644
--- a/src/Uart.bs
+++ b/src/Uart.bs
@@ -32,10 +32,9 @@ data TxState
     Start (Bit 8)
   | -- | The UART is about to send a data bit. 'Data b n' transitions to
     -- 'Data (b >> 1) (n - 1)' by sending a data bit. 'Data b 0' transitions to
-    -- 'Stop' by sending the last data bit.
+    -- 'Idle' by sending the last data bit. Being in the 'Idle' state for a
+    -- clock transmits the stop bit.
     Data (Bit 8) (Bit 3)
-  | -- | The UART is about to send the stop bit. Transitions to 'Idle'.
-    Stop
   deriving (Bits)
 
 -- | The TX side of the UART.
@@ -55,7 +54,9 @@ mkTxUart baudClock bufferSize =
     rules
       "uart_tx": when baudClock.clk
         rules
-          "uart_tx_idle": when Idle <- state ==> do
+          "uart_tx_idle": when Idle <- state, not fifo.notEmpty ==> do
+            pin := 1
+          "uart_tx_idle_to_start": when Idle <- state, fifo.notEmpty ==> do
             pin := 1
             b <- (toGet fifo).get
             state := Start b
@@ -65,12 +66,9 @@ mkTxUart baudClock bufferSize =
           "uart_tx_data": when Data b n <- state ==> do
             pin := b[0:0]
             if n == 0 then
-              state := Stop
+              state := Idle
             else
               state := Data (b >> 1) (n - 1)
-          "uart_tx_stop": when Stop <- state ==> do
-            pin := 1
-            state := Idle
     interface TxUart
       pin = pin
       send = toPut fifo
-- 
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