From eaa9e67b9540bebe980503027d4aa7e6dfd1bf31 Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Fri, 20 Sep 2024 10:03:49 -0500
Subject: Fixed UART.

---
 src/Top.bs    | 25 +++++--------------------
 src/TopSim.bs | 11 +++++++++--
 src/Uart.bs   | 20 ++++++--------------
 3 files changed, 20 insertions(+), 36 deletions(-)

diff --git a/src/Top.bs b/src/Top.bs
index ab2823f..18802bf 100644
--- a/src/Top.bs
+++ b/src/Top.bs
@@ -31,33 +31,19 @@ clockFreqHz = 12_000_000
 mkTop :: Module Top
 mkTop =
   module
-    bitState :: Reg (Bit 1) <- mkReg 0
-    btn2State :: Reg (Bit 1) <- mkReg 0
-    btn3State :: Reg (Bit 1) <- mkReg 0
-
     uart <- mkUart (clockFreqHz / 9600)
-
-    lastByte :: Reg (Bit 8) <- mkReg 0x21
-    tick <- mkDivider (clockFreqHz / 2)
     rules
-      -- "tick": when tick.clk ==> do
-        -- uart.send.put lastByte
-      "debugPin": when True ==> bitState := uart.debugPin
       "recv": when True ==> do
         byte <- uart.recv.get
-        -- lastByte := byte
         uart.send.put byte
-      -- "inc": when tick.clk, btn2State == 1 ==> lastByte := lastByte + 1
-      -- "dec": when tick.clk, btn3State == 1 ==> lastByte := lastByte - 1
 
     interface Top
       -- RS232
-      rx bit = do
-        uart.rxPin bit
+      rx = uart.rxPin
       tx = uart.txPin
       -- Onboard LEDs
       ledR_N = uart.txPin
-      ledG_N = bitState
+      ledG_N = 1
       -- RGB LED driver
       ledRed_N = 1
       ledGrn_N = 1
@@ -68,10 +54,9 @@ mkTop =
       led3 = 0
       led4 = 0
       led5 = 0
-      btn1 1 = lastByte := 0x40
-      btn1 0 = return ()
-      btn2 b = btn2State := b
-      btn3 b = btn3State := b
+      btn1 _ = return ()
+      btn2 _ = return ()
+      btn3 _ = return ()
 {-# verilog mkTop #-}
 {-# properties mkTop = { RSTN = BTN_N } #-}
 
diff --git a/src/TopSim.bs b/src/TopSim.bs
index 0b77d3b..a4f1967 100644
--- a/src/TopSim.bs
+++ b/src/TopSim.bs
@@ -8,13 +8,20 @@ mkTopSim :: Module Empty
 mkTopSim =
   module
     timer :: Reg (Bit 8) <- mkReg 0
+    next :: Reg (Bit 8) <- mkReg 0
+    saved :: Reg (Bit 8) <- mkReg 0x6a
 
     uart <- mkUart 1
 
     rules
       when True ==> timer := timer + 1
-      when True ==> uart.rxPin (1 - uart.txPin)
-      when (timer == 0x00) ==> uart.send.put 0x6a
+      when True ==> uart.rxPin uart.txPin
+      when True ==> do
+        b <- uart.recv.get
+        next := timer + 5
+        saved := b
+      when (timer == next) ==> do
+        uart.send.put saved
       when (timer == 0x40) ==> $finish
 
 -- vim: set ft=haskell :
diff --git a/src/Uart.bs b/src/Uart.bs
index 47d32e0..1059a65 100644
--- a/src/Uart.bs
+++ b/src/Uart.bs
@@ -86,8 +86,8 @@ data RxState
   | -- | In the 'Stop' state, the UART has received the start and data bits,
     -- and is waiting for the stop bit (which is ignored). Transitions to
     -- 'Idle'.
-    Stop
-  deriving (Bits)
+    Stop (Bit 8)
+  deriving (Bits, FShow)
 
 -- | The RX side of the UART.
 interface RxUart =
@@ -96,15 +96,12 @@ interface RxUart =
   -- | Reads a byte from the UART's receive buffer.
   recv :: Get (Bit 8)
 
-  debugPin :: Bit 1
-
 mkRxUart :: Clock -> Integer -> Module RxUart
 mkRxUart baudClock bufferSize =
   module
     fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize
     state :: Reg RxState <- mkReg Idle
     pin :: Wire (Bit 1) <- mkWire
-    debugPin :: Wire (Bit 1) <- mkWire
 
     rules
       "uart_rx": when baudClock.clk
@@ -112,18 +109,16 @@ mkRxUart baudClock bufferSize =
           "uart_rx_idle_to_start": when Idle <- state, pin == 0 ==> do
             state := Data 0 0
           "uart_rx_data_to_data": when Data bits n <- state, n < 7 ==> do
-            state := Data (bits[6:0] ++ pin) (n + 1)
+            state := Data (pin ++ bits[7:1]) (n + 1)
           "uart_rx_data_to_stop": when Data bits 7 <- state ==> do
-            fifo.enq (bits[6:0] ++ pin)
-            state := Stop
-          "uart_rx_stop": when Stop <- state, pin == 1 ==> do
+            state := Stop (pin ++ bits[7:1])
+          "uart_rx_stop_to_idle": when Stop bits <- state, pin == 1 ==> do
+            fifo.enq bits
             state := Idle
-          "debugPin": when True ==> debugPin := if fifo.notEmpty then 1 else 0
 
     interface RxUart
       pin bit = pin := bit
       recv = toGet fifo
-      debugPin = debugPin
 
 -- | An 8n1 UART.
 interface Uart =
@@ -137,8 +132,6 @@ interface Uart =
   -- | Writes a byte to the UART's transmit buffer.
   send :: Put (Bit 8)
 
-  debugPin :: Bit 1
-
 mkUart :: Integer -> Module Uart
 mkUart baudDivisor =
   module
@@ -151,6 +144,5 @@ mkUart baudDivisor =
       txPin = tx.pin
       recv = rx.recv
       send = tx.send
-      debugPin = rx.debugPin
 
 -- vim: set ft=haskell :
-- 
cgit v1.2.3