From 46457cc330049bb38c0af9a3f671b33b8f534c55 Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Wed, 18 Sep 2024 10:14:57 -0500
Subject: Add the simulator.

---
 Makefile | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 8eb9ce6..6b5bd2b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,5 @@
-BSC_COMP_FLAGS = -bdir tmp \
-                 -p src:+ -vdir tmp
-BSC_LINK_FLAGS =
+BSC_COMP_FLAGS = -bdir tmp -p src:+ -simdir tmp -vdir tmp
+BSC_LINK_FLAGS = -bdir tmp -simdir tmp -vdir tmp
 BSC_SOURCES = FIFO1.v FIFO10.v SizedFIFO.v
 TOPFILE = Top
 TOPMODULE = mkTop
@@ -14,8 +13,12 @@ clean:
 	| xargs -0 rm -r
 flash: tmp/$(TOPMODULE).bin
 	sudo iceprog $<
-.PHONY: all clean flash
+gtkwave: tmp/sim.vcd
+	gtkwave $<
+.PHONY: all clean flash gtkwave
 
+tmp/sim.vcd: tmp/$(TOPMODULE)Sim.exe
+	tmp/$(TOPMODULE)Sim.exe -V $@
 tmp/%.bin: tmp/%.asc
 	# icetime -d up5k -c 12 $<
 	icepack $< $@
@@ -24,6 +27,9 @@ tmp/%.asc: tmp/%.json src/icebreaker.pcf
 		--asc $@ --pcf src/icebreaker.pcf --json $<
 tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES))
 	yosys -ql tmp/$(TOPMODULE).yslog -p 'synth_ice40 -top mkTop -json $@' $^
+tmp/$(TOPMODULE)Sim.exe: tmp/$(TOPFILE).bo
+	bsc -u -sim -g $(TOPMODULE)Sim $(BSC_COMP_FLAGS) src/$(TOPFILE)Sim.bs
+	bsc -sim -e $(TOPMODULE)Sim $(BSC_LINK_FLAGS) -o $@
 tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo
 	bsc -g $(TOPMODULE) -verilog $(BSC_COMP_FLAGS) src/$(TOPFILE).bs
 tmp/%.bo:
-- 
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