From 76ce6c75b4bd723aabfd0fd6f4d310d3ed90e7fd Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Wed, 23 Oct 2024 08:24:53 -0500
Subject: checkpoint; something is broken with timing

---
 fpga/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'fpga/Makefile')

diff --git a/fpga/Makefile b/fpga/Makefile
index 8219ab3..ac618b0 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -16,7 +16,7 @@ tmp/%.asc tmp/%-report.json: tmp/%.json src/icebreaker.pcf
 		--asc $@ --report tmp/$*-report.json \
 		--pcf src/icebreaker.pcf --json $<
 tmp/mkTop.json: tmp/mkTop.rewritten.v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES))
-	yosys -ql tmp/mkTop.yslog -p 'synth_ice40 -top mkTop -json $@' $^
+	yosys -ql tmp/mkTop.yslog -p 'synth_ice40 -device u -top mkTop -json $@' $^
 tmp/mkTop.rewritten.v: tmp/mkTop.v
 	cp $< $@
 	perl $(BSC_SRC)/util/scripts/basicinout.pl $@
-- 
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