From 08d727e9886cde6a367906999e96a33f7ba37f33 Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Tue, 8 Oct 2024 14:27:19 -0500
Subject: Reorganization and rewiring.

---
 fpga/src/Clock.bs | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 fpga/src/Clock.bs

(limited to 'fpga/src/Clock.bs')

diff --git a/fpga/src/Clock.bs b/fpga/src/Clock.bs
new file mode 100644
index 0000000..c908502
--- /dev/null
+++ b/fpga/src/Clock.bs
@@ -0,0 +1,19 @@
+-- | A simple clock package.
+package Clock where
+
+interface Clock =
+  clk :: Bool
+
+-- TODO: Make a multiclock that uses one count for all the sub-clocks in the
+-- design.
+
+mkClock :: Bit n -> Module Clock
+mkClock divisor =
+  module
+    count :: Reg (Bit n) <- mkReg 0
+    rules
+      when True ==> count := if count == divisor - 1 then 0 else count + 1
+    interface Clock
+      clk = count == 0
+
+-- vim: set ft=haskell :
-- 
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