From ddf01d51c3429c25a57077d93d3309ce0e5d2262 Mon Sep 17 00:00:00 2001 From: Nathan Ringo Date: Tue, 8 Oct 2024 21:33:12 -0500 Subject: Preparation to start using separate clock domains. --- fpga/src/Clock.bs | 19 ------------------- 1 file changed, 19 deletions(-) delete mode 100644 fpga/src/Clock.bs (limited to 'fpga/src/Clock.bs') diff --git a/fpga/src/Clock.bs b/fpga/src/Clock.bs deleted file mode 100644 index c908502..0000000 --- a/fpga/src/Clock.bs +++ /dev/null @@ -1,19 +0,0 @@ --- | A simple clock package. -package Clock where - -interface Clock = - clk :: Bool - --- TODO: Make a multiclock that uses one count for all the sub-clocks in the --- design. - -mkClock :: Bit n -> Module Clock -mkClock divisor = - module - count :: Reg (Bit n) <- mkReg 0 - rules - when True ==> count := if count == divisor - 1 then 0 else count + 1 - interface Clock - clk = count == 0 - --- vim: set ft=haskell : -- cgit v1.2.3