From ddf01d51c3429c25a57077d93d3309ce0e5d2262 Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Tue, 8 Oct 2024 21:33:12 -0500
Subject: Preparation to start using separate clock domains.

---
 fpga/src/HyperBus.bs | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

(limited to 'fpga/src/HyperBus.bs')

diff --git a/fpga/src/HyperBus.bs b/fpga/src/HyperBus.bs
index 41d1703..2b75b6e 100644
--- a/fpga/src/HyperBus.bs
+++ b/fpga/src/HyperBus.bs
@@ -1,8 +1,6 @@
 -- | A controller for a HyperBus interface, allowing for I/O to four chips.
 package HyperBus where
 
-import Clock
-
 -- | The HyperBus output pins.
 interface HyperBusOut =
   ck       :: Bit 1
@@ -15,11 +13,16 @@ interface HyperBusOut =
   rwds_out :: Maybe (Bit 1)
   dq_out   :: Maybe (Bit 8)
 
-mkHyperBus :: Wire (Bit 1) -> Wire (Bit 8) -> Clock -> Module HyperBusOut
-mkHyperBus rwds_in dq_in clock = module
+mkHyperBus :: Wire (Bit 1) -> Wire (Bit 8) -> Module HyperBusOut
+mkHyperBus rwds_in dq_in = module
+  clockPin :: Reg (Bit 1) <- mkReg 0
+  rules
+    "update_clock_pin": when True ==> do
+      clockPin := invert clockPin
+
   interface HyperBusOut
-    ck = if clock.clk then 1 else 0
-    ck_n = if clock.clk then 0 else 1
+    ck = clockPin
+    ck_n = invert clockPin
     cs0_n = 1
     cs1_n = 1
     cs2_n = 1
-- 
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