From 5088967b9db6e8bcc5feddbea6f53da5b33cb77c Mon Sep 17 00:00:00 2001 From: Nathan Ringo Date: Tue, 24 Sep 2024 00:47:49 -0500 Subject: Another reorg. --- fpga/src/Top.bs | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 6 deletions(-) (limited to 'fpga/src/Top.bs') diff --git a/fpga/src/Top.bs b/fpga/src/Top.bs index 9afaaab..924b19a 100644 --- a/fpga/src/Top.bs +++ b/fpga/src/Top.bs @@ -1,8 +1,12 @@ +-- | The top-level module, for both simulation and the iCEBreaker. package Top where -import App +import Connectable +import CPU +import GetPut import Uart +-- | The interface to the iCEBreaker. interface Top = -- RS232 rx :: Bit 1 -> Action {-# always_enabled, always_ready, prefix = "", arg_names = [RX] #-} @@ -14,6 +18,25 @@ interface Top = ledRed_N :: Bit 1 {-# always_ready, result = LED_RED_N #-} ledGrn_N :: Bit 1 {-# always_ready, result = LED_GRN_N #-} ledBlu_N :: Bit 1 {-# always_ready, result = LED_BLU_N #-} + -- HyperBus 1 (PMOD 1A) + hyperBus_CS2_N :: Bit 1 {-# always_ready, result = P1A1 #-} + hyperBus_CS0_N :: Bit 1 {-# always_ready, result = P1A2 #-} + hyperBus_CK :: Bit 1 {-# always_ready, result = P1A3 #-} + hyperBus_CK_N :: Bit 1 {-# always_ready, result = P1A4 #-} + hyperBus_CS3_N :: Bit 1 {-# always_ready, result = P1A7 #-} + hyperBus_CS1_N :: Bit 1 {-# always_ready, result = P1A8 #-} + hyperBus_RESET_N :: Bit 1 {-# always_ready, result = P1A9 #-} + hyperBus_RWDS :: Bit 1 -> Action {-# always_enabled, always_ready, prefix = "", arg_names = [P1A10] #-} + -- HyperBus 2 (PMOD 1B) + -- hyperBus_DQ0_i :: Bit 1 -> Action {-# always_enabled, always_ready, prefix = "", arg_names = [P1B1] #-} + -- hyperBus_DQ0 :: Inout (Bit 1) {-# always_ready, result = P1B1 #-} + -- hyperBus_DQ1 :: Bit 1 {-# always_ready, result = P1B2 #-} + -- hyperBus_DQ2 :: Bit 1 {-# always_ready, result = P1B3 #-} + -- hyperBus_DQ3 :: Bit 1 {-# always_ready, result = P1B4 #-} + -- hyperBus_DQ7 :: Bit 1 {-# always_ready, result = P1B7 #-} + -- hyperBus_DQ6 :: Bit 1 {-# always_ready, result = P1B8 #-} + -- hyperBus_DQ5 :: Bit 1 {-# always_ready, result = P1B9 #-} + -- hyperBus_DQ4 :: Bit 1 {-# always_ready, result = P1B10 #-} -- LEDs and buttons (PMOD 2) led1 :: Bit 1 {-# always_ready, result = LED1 #-} led2 :: Bit 1 {-# always_ready, result = LED2 #-} @@ -30,8 +53,11 @@ clockFreqHz = 12_000_000 mkTop :: Module Top mkTop = module + cpu <- mkCPU + uart <- mkUart (clockFreqHz / 9600) - app <- mkApp uart.recv uart.send + mkConnection cpu.uart_tx uart.send + mkConnection cpu.uart_rx uart.recv interface Top -- RS232 @@ -39,21 +65,58 @@ mkTop = tx = uart.txPin -- Onboard LEDs ledR_N = uart.txPin - ledG_N = 1 - app.led + ledG_N = 1 -- RGB LED driver ledRed_N = 1 ledGrn_N = 1 ledBlu_N = 1 + -- HyperBus 1 (PMOD 1A) + hyperBus_CS2_N = 1 + hyperBus_CS0_N = 1 + hyperBus_CK = 0 + hyperBus_CK_N = 1 + hyperBus_CS3_N = 1 + hyperBus_CS1_N = 1 + hyperBus_RESET_N = 1 + hyperBus_RWDS _ = noAction -- LEDs and buttons (PMOD 2) led1 = 0 led2 = 0 led3 = 0 led4 = 0 led5 = 0 - btn1 _ = return () - btn2 _ = return () - btn3 _ = return () + btn1 _ = noAction + btn2 _ = noAction + btn3 _ = noAction {-# verilog mkTop #-} {-# properties mkTop = { RSTN = BTN_N } #-} +mkTopSim :: Module Empty +mkTopSim = + module + cpu <- mkCPU + + uart <- mkUart 1 + mkConnection cpu.uart_tx uart.send + mkConnection cpu.uart_rx uart.recv + + fakeUart <- mkUart 1 + rules + when True ==> uart.rxPin fakeUart.txPin + + timer :: Reg (Bit 8) <- mkReg 0 + rules + when True ==> timer := timer + 1 + when (timer == 0x00) ==> fakeUart.send.put 0x30 + when (timer == 0x01) ==> fakeUart.send.put 0x30 + when (timer == 0x02) ==> fakeUart.send.put 0x77 + when (timer == 0x03) ==> fakeUart.send.put 0x31 + when (timer == 0x04) ==> fakeUart.send.put 0x32 + when (timer == 0x05) ==> fakeUart.send.put 0x33 + when (timer == 0x06) ==> fakeUart.send.put 0x34 + when (timer == 0x10) ==> fakeUart.send.put 0x30 + when (timer == 0x11) ==> fakeUart.send.put 0x30 + when (timer == 0x12) ==> fakeUart.send.put 0x72 + when (timer == 0xff) ==> $finish + -- vim: set ft=haskell : -- cgit v1.2.3