From d8db4d5cfa3977001181714e632d5addd7c0e4ba Mon Sep 17 00:00:00 2001 From: Nathan Ringo Date: Mon, 6 May 2024 01:12:26 -0500 Subject: Sending side done! --- src/Top.bs | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'src/Top.bs') diff --git a/src/Top.bs b/src/Top.bs index 2a056ac..d5cb7e3 100644 --- a/src/Top.bs +++ b/src/Top.bs @@ -1,6 +1,7 @@ package Top where -import UART +import GetPut +import Uart interface Top = -- RS232 @@ -30,7 +31,14 @@ mkTop :: Module Top mkTop = module bitState :: Reg (Bit 1) <- mkReg 0 - uart <- mkUART (clockFreqHz / 9600) + + uart <- mkUart (clockFreqHz / 9600) + lastByte :: Reg (Bit 8) <- mkReg 0x21 + + tick <- mkDivider (clockFreqHz) + rules + "tick": when tick.clk ==> do + uart.send.put lastByte interface Top -- RS232 @@ -39,8 +47,8 @@ mkTop = uart.rxPin bit tx = uart.txPin -- Onboard LEDs - ledR_N = uart.txPin - ledG_N = bitState + ledR_N = bitState + ledG_N = uart.txPin -- RGB LED driver ledRed_N = 1 ledGrn_N = 1 @@ -56,3 +64,5 @@ mkTop = btn3 _ = return () {-# verilog mkTop #-} {-# properties mkTop = { RSTN = BTN_N } #-} + +-- vim: set ft=haskell : -- cgit v1.2.3