From d202daead0f05ecb60580fa7be2f23df8c4542fc Mon Sep 17 00:00:00 2001
From: Nathan Ringo <nathan@remexre.com>
Date: Wed, 18 Sep 2024 14:09:34 -0500
Subject: Fix the UART TX.

---
 src/TopSim.bs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/TopSim.bs')

diff --git a/src/TopSim.bs b/src/TopSim.bs
index 5ba7232..93fef14 100644
--- a/src/TopSim.bs
+++ b/src/TopSim.bs
@@ -1,16 +1,23 @@
 package TopSim where
 
+import GetPut
 import Top
+import Uart
 
 mkTopSim :: Module Empty
 mkTopSim =
   module
     timer :: Reg (Bit 8) <- mkReg 0
 
+    uart <- mkUart 1
+
     rules
       when True ==> do
         timer := timer + 1
-      when (timer == 0xff) ==> do
+      when (timer == 0x00) ==> uart.send.put 0x81
+      when (timer == 0x01) ==> uart.send.put 0x18
+      when (timer == 0x02) ==> uart.send.put 0x81
+      when (timer == 0x40) ==> do
         $finish
 
 -- vim: set ft=haskell :
-- 
cgit v1.2.3