BSC_COMP_FLAGS = -bdir tmp \
                 -p src:+ -vdir tmp
BSC_LINK_FLAGS =
BSC_SOURCES = FIFO1.v FIFO10.v SizedFIFO.v
TOPFILE = Top
TOPMODULE = mkTop
SRCS = $(shell find src -name '*.bs')

all: tmp/$(TOPMODULE).bin
clean:
	@git status --porcelain=v1 --ignored -z \
	| grep -z '^!!' \
	| xargs -0 awk 'BEGIN { for(i = 1; i < ARGC; i++) printf "%s%c", substr(ARGV[i], 4), 0; }' \
	| xargs -0 rm -r
flash: tmp/$(TOPMODULE).bin
	sudo iceprog $<
.PHONY: all clean flash

tmp/%.bin: tmp/%.asc
	# icetime -d up5k -c 12 $<
	icepack $< $@
tmp/%.asc: tmp/%.json src/icebreaker.pcf
	nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \
		--asc $@ --pcf src/icebreaker.pcf --json $<
tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES))
	yosys -ql tmp/$(TOPMODULE).yslog -p 'synth_ice40 -top mkTop -json $@' $^
tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo
	bsc -g $(TOPMODULE) -verilog $(BSC_COMP_FLAGS) src/$(TOPFILE).bs
tmp/%.bo:
	@mkdir -p $(dir $@)
	bsc -verilog $(BSC_COMP_FLAGS) $<

tmp/depends.mk:
	@mkdir -p $(dir $@)
	bluetcl -exec makedepend $(BSC_COMP_FLAGS) src/$(TOPFILE).bs > $@
include tmp/depends.mk