BSC_COMP_FLAGS = -bdir tmp -p src:+ -simdir tmp -vdir tmp
BSC_LINK_FLAGS = -bdir tmp -simdir tmp -vdir tmp
BSC_SOURCES = BRAM2.v FIFO1.v FIFO10.v RevertReg.v SizedFIFO.v TriState.v

all: tmp/mkTop.bin
flash: tmp/mkTop.bin
	sudo iceprog $<
gtkwave: tmp/sim.vcd
	gtkwave -A $<
.PHONY: all flash gtkwave

tmp/%.bin: tmp/%.asc
	icepack $< $@
tmp/%.asc tmp/%-report.json: tmp/%.json src/icebreaker.pcf
	nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \
		--asc $@ --report tmp/$*-report.json \
		--pcf src/icebreaker.pcf --json $<
tmp/mkTop.json: tmp/mkTop.rewritten.v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES))
	yosys -ql tmp/mkTop.yslog -p 'synth_ice40 -top mkTop -json $@' $^
tmp/mkTop.rewritten.v: tmp/mkTop.v
	cp $< $@
	perl $(BSC_SRC)/util/scripts/basicinout.pl $@
tmp/mkTop.v:
	@mkdir -p $(dir $@)
	bsc -u -verilog -g mkTop $(BSC_COMP_FLAGS) src/Top.bs

tmp/sim.vcd: tmp/mkTopSim.exe
	tmp/mkTopSim.exe -V $@
tmp/mkTopSim.exe: tmp/mkTopSim.ba
	bsc -sim -e mkTopSim $(BSC_LINK_FLAGS) -o $@
tmp/mkTopSim.ba:
	@mkdir -p $(dir $@)
	bsc -u -sim -g mkTopSim $(BSC_COMP_FLAGS) src/Top.bs

.PHONY: tmp/mkTop.v tmp/mkTopSim.ba