1 files changed, 33 insertions, 17 deletions
diff --git a/boards/qemu-virt/qemu-virt.s b/boards/qemu-virt/qemu-virt.s
index 0d69d4d..bd32676 100644
--- a/boards/qemu-virt/qemu-virt.s
+++ b/boards/qemu-virt/qemu-virt.s
@@ -1,5 +1,5 @@
-.extern main
-.extern CONSOLE_STRICT_FLUSH
+.extern hart0_boot
+.extern hart0_early_boot
 
 .section .text.start
 
@@ -11,18 +11,6 @@ _start:
 	csrr tp, mhartid
 	bnez tp, wait_for_hart0
 
-	## Set up hart0's stack.
-	la sp, hart0_initial_stack_top
-
-	## Write a canary to hart0's stack.
-	li t0, 0xdead0bad0defaced
-	la t1, hart0_initial_stack
-	sd t0, (t1)
-
-	## Put the address of the DeviceTree into the first argument position
-	## for hart0_boot.
-	c.mv a0, a1
-
 ### Set up trap handling.
 
 	## Set MENVCFG.STCE, to enable the Sstc extension, which will allow us
@@ -55,9 +43,9 @@ _start:
 	li t0, 0b01 << 11
 	csrs mstatus, t0
 
-	## Next, set MEPC to the address of hart0_boot, so that when we execute
-	## mret, execution will continue there.
-	la t0, hart0_boot
+	## Next, set MEPC to the address of hart0_full_boot, so that when we
+	## execute mret, execution will continue there.
+	la t0, hart0_full_boot
 	csrw mepc, t0
 
 	## Set SATP.MODE to Bare, and clear the rest of the bits. This disables
@@ -78,6 +66,34 @@ _start:
 
 .section .text
 
+.type hart0_full_boot, STT_FUNC
+hart0_full_boot:
+	## Set up hart0's stack.
+	la sp, hart0_initial_stack_top
+
+	## Write a canary to hart0's stack.
+	li t0, 0xdead0bad0defaced
+	la t1, hart0_initial_stack
+	sd t0, (t1)
+
+	## Call hart0_early_boot, passing it the DeviceTree we received and
+	## getting back the address of a stack to switch to.
+	mv a0, a1
+	call hart0_early_boot
+
+	## Switch to the returned stack.
+	mv sp, a0
+
+	## Load the canary back from hart0's stack.
+	la t0, hart0_initial_stack
+	ld a0, (t0)
+
+	## Jump to hart0_boot.
+	j hart0_boot
+.size hart0_full_boot, . - hart0_full_boot
+
+.section .text
+
 .type wait_for_hart0, STT_FUNC
 wait_for_hart0:
 	# TODO