Start of an application.

4 files changed, 77 insertions, 18 deletions

diff --git a/Makefile b/Makefile
index 4eeeae1..2d1d292 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 BSC_COMP_FLAGS = -bdir tmp -p src:+ -simdir tmp -vdir tmp
 BSC_LINK_FLAGS = -bdir tmp -simdir tmp -vdir tmp
-BSC_SOURCES = FIFO1.v FIFO10.v SizedFIFO.v
+BSC_SOURCES = BRAM2.v FIFO1.v FIFO10.v RevertReg.v SizedFIFO.v
 TOPFILE = Top
 TOPMODULE = mkTop
 SRCS = $(shell find src -name '*.bs')
diff --git a/src/App.bs b/src/App.bs
new file mode 100644
index 0000000..5b48b2b
--- /dev/null
+++ b/src/App.bs
@@ -0,0 +1,66 @@
+package App where
+
+-- import BRAM
+    -- ebrServer1 :: BRAM2Port (Bit 8) (Bit 16) <- mkBRAM2Server defaultValue
+import GetPut
+
+interface App =
+  led :: Bit 1
+
+hexToBits :: Bit 8 -> Maybe (Bit 4)
+hexToBits 0x30 = Just 0b0000
+hexToBits 0x31 = Just 0b0001
+hexToBits 0x32 = Just 0b0010
+hexToBits 0x33 = Just 0b0011
+hexToBits 0x34 = Just 0b0100
+hexToBits 0x35 = Just 0b0101
+hexToBits 0x36 = Just 0b0110
+hexToBits 0x37 = Just 0b0111
+hexToBits 0x38 = Just 0b1000
+hexToBits 0x39 = Just 0b1001
+hexToBits 0x41 = Just 0b1010
+hexToBits 0x42 = Just 0b1011
+hexToBits 0x43 = Just 0b1100
+hexToBits 0x44 = Just 0b1101
+hexToBits 0x45 = Just 0b1110
+hexToBits 0x46 = Just 0b1111
+hexToBits 0x61 = Just 0b1010
+hexToBits 0x62 = Just 0b1011
+hexToBits 0x63 = Just 0b1100
+hexToBits 0x64 = Just 0b1101
+hexToBits 0x65 = Just 0b1110
+hexToBits 0x66 = Just 0b1111
+hexToBits _ = Nothing
+
+data State
+  = WaitingForHiNybble
+  | WaitingForLoNybble (Bit 4)
+  deriving (Bits)
+
+mkApp :: Get (Bit 8) -> Put (Bit 8) -> Module App
+mkApp uartRecv uartSend =
+  module
+    led :: Reg (Bit 1) <- mkReg 0
+    state :: Reg State <- mkReg WaitingForHiNybble
+
+    rules
+      "get_hi_nybble": when WaitingForHiNybble <- state ==> do
+        byte <- uartRecv.get
+        case hexToBits byte of
+          Just hiNybble -> do
+            state := WaitingForLoNybble hiNybble
+            led := 1
+          Nothing -> return ()
+      "get_lo_nybble": when WaitingForLoNybble hiNybble <- state ==> do
+        byte <- uartRecv.get
+        case hexToBits byte of
+          Just loNybble -> do
+            uartSend.put (hiNybble ++ loNybble)
+            state := WaitingForHiNybble
+            led := 0
+          Nothing -> return ()
+
+    interface App
+      led = led
+
+-- vim: set ft=haskell :
diff --git a/src/Top.bs b/src/Top.bs
index 18802bf..9afaaab 100644
--- a/src/Top.bs
+++ b/src/Top.bs
@@ -1,7 +1,6 @@
 package Top where
 
-import FIFOF
-import GetPut
+import App
 import Uart
 
 interface Top =
@@ -32,10 +31,7 @@ mkTop :: Module Top
 mkTop =
   module
     uart <- mkUart (clockFreqHz / 9600)
-    rules
-      "recv": when True ==> do
-        byte <- uart.recv.get
-        uart.send.put byte
+    app <- mkApp uart.recv uart.send
 
     interface Top
       -- RS232
@@ -43,7 +39,7 @@ mkTop =
       tx = uart.txPin
       -- Onboard LEDs
       ledR_N = uart.txPin
-      ledG_N = 1
+      ledG_N = 1 - app.led
       -- RGB LED driver
       ledRed_N = 1
       ledGrn_N = 1
diff --git a/src/TopSim.bs b/src/TopSim.bs
index a4f1967..0db5c10 100644
--- a/src/TopSim.bs
+++ b/src/TopSim.bs
@@ -1,27 +1,24 @@
 package TopSim where
 
+import App
 import GetPut
-import Top
 import Uart
 
 mkTopSim :: Module Empty
 mkTopSim =
   module
     timer :: Reg (Bit 8) <- mkReg 0
-    next :: Reg (Bit 8) <- mkReg 0
-    saved :: Reg (Bit 8) <- mkReg 0x6a
 
     uart <- mkUart 1
+    app <- mkApp uart.recv uart.send
+
+    fakeUart <- mkUart 1
 
     rules
       when True ==> timer := timer + 1
-      when True ==> uart.rxPin uart.txPin
-      when True ==> do
-        b <- uart.recv.get
-        next := timer + 5
-        saved := b
-      when (timer == next) ==> do
-        uart.send.put saved
+      when True ==> uart.rxPin fakeUart.txPin
+      when (timer == 0x00) ==> fakeUart.send.put 0x30
+      when (timer == 0x01) ==> fakeUart.send.put 0x31
       when (timer == 0x40) ==> $finish
 
 -- vim: set ft=haskell :