Add the simulator.

4 files changed, 36 insertions, 9 deletions

diff --git a/.gitignore b/.gitignore
index 732ff23..0900006 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,4 +11,3 @@ result-*
 
 # Non-Nix outputs
 tmp/
-dump.vcd
diff --git a/Makefile b/Makefile
index 8eb9ce6..6b5bd2b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,5 @@
-BSC_COMP_FLAGS = -bdir tmp \
-                 -p src:+ -vdir tmp
-BSC_LINK_FLAGS =
+BSC_COMP_FLAGS = -bdir tmp -p src:+ -simdir tmp -vdir tmp
+BSC_LINK_FLAGS = -bdir tmp -simdir tmp -vdir tmp
 BSC_SOURCES = FIFO1.v FIFO10.v SizedFIFO.v
 TOPFILE = Top
 TOPMODULE = mkTop
@@ -14,8 +13,12 @@ clean:
 	| xargs -0 rm -r
 flash: tmp/$(TOPMODULE).bin
 	sudo iceprog $<
-.PHONY: all clean flash
+gtkwave: tmp/sim.vcd
+	gtkwave $<
+.PHONY: all clean flash gtkwave
 
+tmp/sim.vcd: tmp/$(TOPMODULE)Sim.exe
+	tmp/$(TOPMODULE)Sim.exe -V $@
 tmp/%.bin: tmp/%.asc
 	# icetime -d up5k -c 12 $<
 	icepack $< $@
@@ -24,6 +27,9 @@ tmp/%.asc: tmp/%.json src/icebreaker.pcf
 		--asc $@ --pcf src/icebreaker.pcf --json $<
 tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES))
 	yosys -ql tmp/$(TOPMODULE).yslog -p 'synth_ice40 -top mkTop -json $@' $^
+tmp/$(TOPMODULE)Sim.exe: tmp/$(TOPFILE).bo
+	bsc -u -sim -g $(TOPMODULE)Sim $(BSC_COMP_FLAGS) src/$(TOPFILE)Sim.bs
+	bsc -sim -e $(TOPMODULE)Sim $(BSC_LINK_FLAGS) -o $@
 tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo
 	bsc -g $(TOPMODULE) -verilog $(BSC_COMP_FLAGS) src/$(TOPFILE).bs
 tmp/%.bo:
diff --git a/src/TopSim.bs b/src/TopSim.bs
new file mode 100644
index 0000000..5ba7232
--- /dev/null
+++ b/src/TopSim.bs
@@ -0,0 +1,16 @@
+package TopSim where
+
+import Top
+
+mkTopSim :: Module Empty
+mkTopSim =
+  module
+    timer :: Reg (Bit 8) <- mkReg 0
+
+    rules
+      when True ==> do
+        timer := timer + 1
+      when (timer == 0xff) ==> do
+        $finish
+
+-- vim: set ft=haskell :
diff --git a/src/Uart.bs b/src/Uart.bs
index adf77d4..f66970c 100644
--- a/src/Uart.bs
+++ b/src/Uart.bs
@@ -83,8 +83,12 @@ data RxState
   | -- | In the 'Data _ n' state, the UART has received the start bit and 'n'
     -- data bits, and is about to receive more data bits. 'Data _ n'
     -- transitions to 'Data _ (n + 1)' by receiving a data bit. 'Data b 7'
-    -- transitions to 'Idle' by receving the last data bit.
+    -- transitions to 'Stop' by receving the last data bit.
     Data (Bit 8) (Bit 3)
+  | -- | In the 'Stop' state, the UART has received the start and data bits,
+    -- and is waiting for the stop bit (which is ignored). Transitions to
+    -- 'Idle'.
+    Stop
   deriving (Bits)
 
 -- | The RX side of the UART.
@@ -109,7 +113,7 @@ mkRxUart baudClock bufferSize =
         rules
           "uart_rx_idle": when Idle <- state ==>
             if pin == 0 then do
-              debugBit := 0
+              debugBit := pin
               state := Data 0 0
             else
               state := Idle
@@ -117,10 +121,12 @@ mkRxUart baudClock bufferSize =
             let newBits = pin ++ oldBits[6:0]
             if n == 7 then do
               fifo.enq newBits
-              debugBit := 1
-              state := Idle
+              state := Stop
             else
               state := Data newBits (n + 1)
+          "uart_rx_stop": when Stop <- state ==> do
+            debugBit := pin
+            state := Idle
 
     interface RxUart
       pin bit = pin := bit