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authorNathan Ringo <nathan@remexre.com>2024-10-23 18:08:47 -0500
committerNathan Ringo <nathan@remexre.com>2024-10-23 18:08:47 -0500
commit5cf952244aac59e5eec4f789e8b4261967c7055a (patch)
tree08910400d89cb7456bab4df9a0ce5cbd40782a3a /fpga/src/TopSim.bs
parentee38cf7feceef308fd0fcbca89f1e7f76714bd62 (diff)
like 1/3 of an i2c ctrler
Diffstat (limited to 'fpga/src/TopSim.bs')
-rw-r--r--fpga/src/TopSim.bs31
1 files changed, 15 insertions, 16 deletions
diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs
index 322ffb2..d4a5812 100644
--- a/fpga/src/TopSim.bs
+++ b/fpga/src/TopSim.bs
@@ -20,27 +20,26 @@ mkTopSim = module
hyperbus_rwds_in hyperbus_dq_in i2c_scl_in i2c_sda_in
-}
- i2c_scl <- mkReg 0
- i2c_sda <- mkReg 0
- -- i2c <- mkDividedI2C (12_000_000 / 200_000) 1 1
- -- i2c <- mkDividedI2C 2 1 1
- i2c <- mkI2C 1 1
+ txSCL <- mkReg 0
+ txSDA <- mkReg 0
+ rxSCL <- mkReg 1
+ rxSDA <- mkReg 1
+ i2c <- mkI2C rxSCL rxSDA
rules
- when True ==> i2c_scl := i2c.txSCL
- when True ==> i2c_sda := i2c.txSDA
+ when True ==> txSCL := i2c.txSCL
+ when True ==> txSDA := i2c.txSDA
timer :: Reg (Bit 16) <- mkReg 0
rules
- {-
- "t0": when (timer == 0) ==> i2c.send.put (Write 0x20 0x00)
- "t1": when (timer == 1) ==> i2c.send.put (Write 0x20 0x00)
- "t2": when (timer == 2) ==> i2c.send.put (Write 0x20 0x00)
- "t3": when (timer == 3) ==> i2c.send.put (Write 0x20 0x12)
- "t4": when (timer == 4) ==> i2c.send.put (Write 0x20 0xaa)
- "t5": when (timer == 5) ==> i2c.send.put (Write 0x20 0x55)
- -}
+ "t0000": when (timer == 0x0000) ==> do
+ i2c.addrReg := 0x01
+ i2c.dataReg := 0x00
+ "t0001": when (timer == 0x0001) ==> do
+ i2c.statusReg := i2c.statusReg { notBusy = True }
+ "t0022": when (timer == 0x0022) ==> rxSDA := 0
+ "t0025": when (timer == 0x0025) ==> rxSDA := 1
"advance timer": when True ==> timer := timer + 1
- "finish": when (timer == 0x1fff) ==> $finish
+ "finish": when (timer == 0x00ff) ==> $finish
{-
"log received values": when True ==> do
result <- i2c.recv.get