diff options
| author | Nathan Ringo <nathan@remexre.com> | 2024-10-24 19:31:34 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-24 19:31:34 -0500 |
| commit | 97723bb6471ce74a8e69e79fda4410b0c53329a2 (patch) | |
| tree | c133552b70375f885893585b3e7f93eefd033319 /fpga/src/TopSim.bs | |
| parent | 2d7d2d10a98f3773db6428235d86408ddb48a33d (diff) | |
Completed read?
Diffstat (limited to 'fpga/src/TopSim.bs')
| -rw-r--r-- | fpga/src/TopSim.bs | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs index d4a5812..4721a42 100644 --- a/fpga/src/TopSim.bs +++ b/fpga/src/TopSim.bs @@ -32,12 +32,17 @@ mkTopSim = module timer :: Reg (Bit 16) <- mkReg 0 rules "t0000": when (timer == 0x0000) ==> do - i2c.addrReg := 0x01 + i2c.addrReg := 0x20 ++ (1 :: Bit 1) i2c.dataReg := 0x00 "t0001": when (timer == 0x0001) ==> do - i2c.statusReg := i2c.statusReg { notBusy = True } - "t0022": when (timer == 0x0022) ==> rxSDA := 0 - "t0025": when (timer == 0x0025) ==> rxSDA := 1 + i2c.statusReg := i2c.statusReg { ready = False; dataAckBit = False } + "t0022": when (timer == 0x0023) ==> rxSDA := 0 + "t0025": when (timer == 0x0027) ==> rxSDA := 1 + "t0049": when (timer == 0x0049) ==> do + i2c.addrReg := 0x20 ++ (0 :: Bit 1) + i2c.dataReg := 0x00 + "t004a": when (timer == 0x004a) ==> do + i2c.statusReg := i2c.statusReg { ready = False } "advance timer": when True ==> timer := timer + 1 "finish": when (timer == 0x00ff) ==> $finish {- |