diff options
| author | Nathan Ringo <nathan@remexre.com> | 2024-10-24 21:37:09 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-24 21:37:09 -0500 |
| commit | d3bcde4eedd2dd3dcf5cbc4302821f38ff553498 (patch) | |
| tree | 504e0122bafe4230ec6ff9c05f2afc8b19bc338e /fpga/src/TopSim.bs | |
| parent | 7d5d900b63103469e9592e365031a979a24c95f6 (diff) | |
Single writes working?
Diffstat (limited to 'fpga/src/TopSim.bs')
| -rw-r--r-- | fpga/src/TopSim.bs | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs index c512edc..e4e65c9 100644 --- a/fpga/src/TopSim.bs +++ b/fpga/src/TopSim.bs @@ -32,17 +32,19 @@ mkTopSim = module timer :: Reg (Bit 16) <- mkReg 0 rules "t0000": when (timer == 0x0000) ==> do - i2c.addrReg := 0x20 ++ (1 :: Bit 1) - i2c.dataReg := 0x00 + i2c.addrReg := 0x20 ++ (0 :: Bit 1) + i2c.dataReg := 0x12 "t0001": when (timer == 0x0001) ==> do i2c.statusReg := i2c.statusReg { ready = False; dataAckBit = True } + "t0002": when (timer == 0x0002) ==> do + i2c.addrReg := 0x20 ++ (0 :: Bit 1) + i2c.dataReg := 0xaa "t0022": when (timer == 0x0023) ==> rxSDA := 0 "t0025": when (timer == 0x0027) ==> rxSDA := 1 - "t0049": when (timer == 0x0049) ==> do - i2c.addrReg := 0x20 ++ (0 :: Bit 1) - i2c.dataReg := 0x00 - "t004a": when (timer == 0x004a) ==> do - i2c.statusReg := i2c.statusReg { ready = False } + -- "t0047": when (timer == 0x0047) ==> rxSDA := 0 + -- "t0051": when (timer == 0x004b) ==> rxSDA := 1 + -- "t004b": when (timer == 0x004b) ==> do + -- i2c.statusReg := i2c.statusReg { ready = False } "advance timer": when True ==> timer := timer + 1 "finish": when (timer == 0x00ff) ==> $finish {- |