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| author | Nathan Ringo <nathan@remexre.com> | 2024-10-08 10:08:58 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-08 10:08:58 -0500 |
| commit | ed3e96b5eaae71d035e14569b107040c3538f849 (patch) | |
| tree | 3048185cb141632a0553979f51ac1c05f2a7cb58 /fpga/src/TopSim.bs | |
| parent | 37507ecea3277a99e60c7bb077c6cd406bb80ddb (diff) | |
Split the simulator back out to its own package.
This ensures that the presence of Inouts doesn't make Bluesim mad.
Diffstat (limited to 'fpga/src/TopSim.bs')
| -rw-r--r-- | fpga/src/TopSim.bs | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs new file mode 100644 index 0000000..ca92fe1 --- /dev/null +++ b/fpga/src/TopSim.bs @@ -0,0 +1,38 @@ +-- | The top-level module for simulation. +package TopSim where + +import Connectable +import CPU +import GetPut +import TriState +import Uart + +mkTopSim :: Module Empty +mkTopSim = + module + cpu <- mkCPU + + uart <- mkUart 1 + mkConnection cpu.uart_tx uart.send + mkConnection cpu.uart_rx uart.recv + + fakeUart <- mkUart 1 + rules + when True ==> uart.rxPin fakeUart.txPin + + timer :: Reg (Bit 8) <- mkReg 0 + rules + when True ==> timer := timer + 1 + when (timer == 0x00) ==> fakeUart.send.put 0x30 + when (timer == 0x01) ==> fakeUart.send.put 0x30 + when (timer == 0x02) ==> fakeUart.send.put 0x77 + when (timer == 0x03) ==> fakeUart.send.put 0x31 + when (timer == 0x04) ==> fakeUart.send.put 0x32 + when (timer == 0x05) ==> fakeUart.send.put 0x33 + when (timer == 0x06) ==> fakeUart.send.put 0x34 + when (timer == 0x10) ==> fakeUart.send.put 0x30 + when (timer == 0x11) ==> fakeUart.send.put 0x30 + when (timer == 0x12) ==> fakeUart.send.put 0x72 + when (timer == 0xff) ==> $finish + +-- vim: set ft=haskell : |