Reorganization and rewiring.

1 files changed, 19 insertions, 46 deletions

diff --git a/fpga/src/Uart.bs b/fpga/src/Uart.bs
index b54cfb8..7298083 100644
--- a/fpga/src/Uart.bs
+++ b/fpga/src/Uart.bs
@@ -1,26 +1,9 @@
 package Uart where
 
+import Clock
 import FIFOF
 import GetPut
 
-interface Clock =
-  clk :: Bool
-
-mkDivider :: Integer -> Module Clock
-mkDivider divisor =
-  module
-    count :: Reg (Bit 32) <- mkReg 0
-
-    rules
-      "increment_divider": when True ==> do
-        if count == fromInteger (divisor - 1) then do
-          count := 0
-        else
-          count := count + 1
-
-    interface Clock
-      clk = count == 0
-
 -- | The state of the TX side of the UART.
 data TxState
   = -- | The UART is not currently sending anything. May transition to
@@ -44,14 +27,14 @@ interface TxUart =
   send :: Put (Bit 8)
 
 mkTxUart :: Clock -> Integer -> Module TxUart
-mkTxUart baudClock bufferSize =
+mkTxUart clock bufferSize =
   module
     fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize
     state :: Reg TxState <- mkReg Idle
     pin :: Reg (Bit 1) <- mkReg 1
 
     rules
-      "uart_tx": when baudClock.clk
+      "uart_tx": when clock.clk
         rules
           "uart_tx_idle": when Idle <- state, not fifo.notEmpty ==> do
             pin := 1
@@ -90,58 +73,48 @@ data RxState
 
 -- | The RX side of the UART.
 interface RxUart =
-  -- | The RX pin.
-  pin :: Bit 1 -> Action
   -- | Reads a byte from the UART's receive buffer.
   recv :: Get (Bit 8)
 
-mkRxUart :: Clock -> Integer -> Module RxUart
-mkRxUart baudClock bufferSize =
+mkRxUart :: Wire (Bit 1) -> Clock -> Integer -> Module RxUart
+mkRxUart rx clock bufferSize =
   module
     fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize
     state :: Reg RxState <- mkReg Idle
-    pin :: Wire (Bit 1) <- mkWire
 
     rules
-      "uart_rx": when baudClock.clk
+      "uart_rx": when clock.clk
         rules
-          "uart_rx_idle_to_start": when Idle <- state, pin == 0 ==> do
+          "uart_rx_idle_to_start": when Idle <- state, rx == 0 ==> do
             state := Data 0 0
           "uart_rx_data_to_data": when Data bits n <- state, n < 7 ==> do
-            state := Data (pin ++ bits[7:1]) (n + 1)
+            state := Data (rx ++ bits[7:1]) (n + 1)
           "uart_rx_data_to_stop": when Data bits 7 <- state ==> do
-            state := Stop (pin ++ bits[7:1])
-          "uart_rx_stop_to_idle": when Stop bits <- state, pin == 1 ==> do
+            state := Stop (rx ++ bits[7:1])
+          "uart_rx_stop_to_idle": when Stop bits <- state, rx == 1 ==> do
             fifo.enq bits
             state := Idle
 
     interface RxUart
-      pin bit = pin := bit
       recv = toGet fifo
 
 -- | An 8n1 UART.
 interface Uart =
-  -- | The RX pin.
-  rxPin :: Bit 1 -> Action
   -- | The TX pin.
-  txPin :: Bit 1
+  tx :: Bit 1
 
   -- | Reads a byte from the UART's receive buffer.
   recv :: Get (Bit 8)
   -- | Writes a byte to the UART's transmit buffer.
   send :: Put (Bit 8)
 
-mkUart :: Integer -> Module Uart
-mkUart baudDivisor =
-  module
-    baudClock <- mkDivider baudDivisor
-    rx <- mkRxUart baudClock 8
-    tx <- mkTxUart baudClock 8
-
-    interface Uart
-      rxPin = rx.pin
-      txPin = tx.pin
-      recv = rx.recv
-      send = tx.send
+mkUart :: Wire (Bit 1) -> Clock -> Module Uart
+mkUart rx clock = module
+  uart_rx <- mkRxUart rx clock 8
+  uart_tx <- mkTxUart clock 8
+  interface Uart
+    tx = uart_tx.pin
+    recv = uart_rx.recv
+    send = uart_tx.send
 
 -- vim: set ft=haskell :