refactor, but now the timing fails again...

1 files changed, 3 insertions, 13 deletions

diff --git a/src/Top.bs b/src/Top.bs
index 7182a98..ec043c9 100644
--- a/src/Top.bs
+++ b/src/Top.bs
@@ -34,9 +34,7 @@ mkTop =
     bitState :: Reg (Bit 1) <- mkReg 0
 
     uart <- mkUart (clockFreqHz / 9600)
-    btn1State :: Reg (Bit 1) <- mkReg 0
 
-    {-
     lastByte :: Reg (Bit 8) <- mkReg 0x21
     tick <- mkDivider (clockFreqHz)
     rules
@@ -45,13 +43,6 @@ mkTop =
       "recv": when tick.clk ==> do
         byte <- uart.recv.get
         lastByte := byte
-    -}
-    rules
-      -- "echo": when True ==> do
-        -- byte <- uart.recv.get
-        -- uart.send.put byte
-      "say_one": when btn1State /= 0 ==> do
-        uart.send.put 0x31
 
     interface Top
       -- RS232
@@ -60,8 +51,8 @@ mkTop =
         uart.rxPin bit
       tx = uart.txPin
       -- Onboard LEDs
-      ledR_N = 1
-      ledG_N = uart.debugBit
+      ledR_N = uart.txPin
+      ledG_N = uart.txPin
       -- RGB LED driver
       ledRed_N = 1
       ledGrn_N = 1
@@ -72,8 +63,7 @@ mkTop =
       led3 = 0
       led4 = 0
       led5 = 0
-      btn1 bit = do
-        btn1State := bit
+      btn1 _ = return ()
       btn2 _ = return ()
       btn3 _ = return ()
 {-# verilog mkTop #-}