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authorNathan Ringo <nathan@remexre.com>2024-05-05 22:30:50 -0500
committerNathan Ringo <nathan@remexre.com>2024-05-05 22:30:50 -0500
commitf9b73dc7b93bbf60f5b2281a5056c4339e049388 (patch)
tree5325a2e6ee78bb36179c5b2b4c56da806214e426 /src/Top.bs
parent0874c7f1852145c3ae62f1e28dc10c0c89d78b45 (diff)
triyng a uart from scratch... not yet working...
Diffstat (limited to 'src/Top.bs')
-rw-r--r--src/Top.bs54
1 files changed, 17 insertions, 37 deletions
diff --git a/src/Top.bs b/src/Top.bs
index 61bdc86..2a056ac 100644
--- a/src/Top.bs
+++ b/src/Top.bs
@@ -1,7 +1,6 @@
package Top where
-import GetPut
-import RS232
+import UART
interface Top =
-- RS232
@@ -30,49 +29,30 @@ clockFreqHz = 12_000_000
mkTop :: Module Top
mkTop =
module
- let uartBaud :: Integer
- uartBaud = 115200
- uartDivider :: Integer
- uartDivider = clockFreqHz / uartBaud
- uart :: UART 8 <- mkUART 8 NONE STOP_1 (fromInteger uartDivider)
-
- clkState :: Reg (Bit 32) <- mkReg 0
- btn1State :: Reg (Bit 1) <- mkReg 0
- btn2State :: Reg (Bit 1) <- mkReg 0
- btn3State :: Reg (Bit 1) <- mkReg 0
- led4State :: Reg (Bit 1) <- mkReg 0
- led5State :: Reg (Bit 1) <- mkReg 0
-
- rules
- "echo": when (clkState == 0) ==> do
- led4State := led4State + 1
- uart.rx.put 0x7e
- "increment_clock": when True ==> do
- if clkState == fromInteger (clockFreqHz / 10) then do
- clkState := 0
- led5State := led5State + 1
- else
- clkState := clkState + 1
+ bitState :: Reg (Bit 1) <- mkReg 0
+ uart <- mkUART (clockFreqHz / 9600)
interface Top
-- RS232
- rx = uart.rs232.sin
- tx = uart.rs232.sout
+ rx bit = do
+ bitState := bit
+ uart.rxPin bit
+ tx = uart.txPin
-- Onboard LEDs
- ledR_N = 1
- ledG_N = 1
+ ledR_N = uart.txPin
+ ledG_N = bitState
-- RGB LED driver
ledRed_N = 1
ledGrn_N = 1
ledBlu_N = 1
-- LEDs and buttons (PMOD 2)
- led1 = btn1State
- led2 = btn2State
- led3 = btn3State
- led4 = led4State
- led5 = led5State
- btn1 x = btn1State := x
- btn2 x = btn2State := x
- btn3 x = btn3State := x
+ led1 = 0
+ led2 = 0
+ led3 = 0
+ led4 = 0
+ led5 = 0
+ btn1 _ = return ()
+ btn2 _ = return ()
+ btn3 _ = return ()
{-# verilog mkTop #-}
{-# properties mkTop = { RSTN = BTN_N } #-}