tweak debug, why is it always enqueueing a zero...

1 files changed, 8 insertions, 7 deletions

diff --git a/src/Uart.bs b/src/Uart.bs
index 2cfe14a..adf77d4 100644
--- a/src/Uart.bs
+++ b/src/Uart.bs
@@ -99,7 +99,7 @@ interface RxUart =
 mkRxUart :: Clock -> Integer -> Module RxUart
 mkRxUart baudClock bufferSize =
   module
-    fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize
+    fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize
     state :: Reg RxState <- mkReg Idle
     pin :: Wire (Bit 1) <- mkWire
     debugBit :: Reg (Bit 1) <- mkReg 1
@@ -108,18 +108,19 @@ mkRxUart baudClock bufferSize =
       "uart_rx": when baudClock.clk
         rules
           "uart_rx_idle": when Idle <- state ==>
-            if pin == 0 then
+            if pin == 0 then do
+              debugBit := 0
               state := Data 0 0
             else
               state := Idle
-          "uart_rx_data": when Data hi n <- state ==> do
-            debugBit := pin
-            let b :: Bit 8 = hi[7:1] ++ pin
+          "uart_rx_data": when Data oldBits n <- state ==> do
+            let newBits = pin ++ oldBits[6:0]
             if n == 7 then do
-              fifo.enq b
+              fifo.enq newBits
+              debugBit := 1
               state := Idle
             else
-              state := Data b (n + 1)
+              state := Data newBits (n + 1)
 
     interface RxUart
       pin bit = pin := bit