diff options
| -rw-r--r-- | Makefile | 4 | ||||
| -rw-r--r-- | src/Top.bs | 16 | ||||
| -rw-r--r-- | src/Uart.bs | 27 |
3 files changed, 29 insertions, 18 deletions
@@ -1,6 +1,6 @@ -BSC_COMP_FLAGS = -aggressive-conditions -bdir tmp -check-assert -keep-fires \ +BSC_COMP_FLAGS = -bdir tmp \ -p src:+ -vdir tmp -BSC_LINK_FLAGS = -keep-fires +BSC_LINK_FLAGS = BSC_SOURCES = FIFO1.v FIFO10.v SizedFIFO.v TOPFILE = Top TOPMODULE = mkTop @@ -34,6 +34,7 @@ mkTop = bitState :: Reg (Bit 1) <- mkReg 0 uart <- mkUart (clockFreqHz / 9600) + btn1State :: Reg (Bit 1) <- mkReg 0 {- lastByte :: Reg (Bit 8) <- mkReg 0x21 @@ -46,9 +47,11 @@ mkTop = lastByte := byte -} rules - "echo": when True ==> do - byte <- uart.recv.get - uart.send.put byte + -- "echo": when True ==> do + -- byte <- uart.recv.get + -- uart.send.put byte + "say_one": when btn1State /= 0 ==> do + uart.send.put 0x31 interface Top -- RS232 @@ -57,8 +60,8 @@ mkTop = uart.rxPin bit tx = uart.txPin -- Onboard LEDs - ledR_N = bitState - ledG_N = uart.bit + ledR_N = 1 + ledG_N = uart.debugBit -- RGB LED driver ledRed_N = 1 ledGrn_N = 1 @@ -69,7 +72,8 @@ mkTop = led3 = 0 led4 = 0 led5 = 0 - btn1 _ = return () + btn1 bit = do + btn1State := bit btn2 _ = return () btn3 _ = return () {-# verilog mkTop #-} diff --git a/src/Uart.bs b/src/Uart.bs index d6918f9..182236d 100644 --- a/src/Uart.bs +++ b/src/Uart.bs @@ -91,26 +91,28 @@ interface RxUart = -- | Reads a byte from the UART's receive buffer. recv :: Get (Bit 8) - bit :: Bit 1 + debugBit :: Bit 1 mkRxUart :: Clock -> Integer -> Module RxUart mkRxUart baudClock bufferSize = module - fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize + fifo :: FIFOF (Bit 8) <- mkUGSizedFIFOF bufferSize state :: Reg RxState <- mkReg Idle - debug :: Reg (Bit 1) <- mkReg 1 + debugBit :: Reg (Bit 1) <- mkReg 1 interface RxUart pin bit = when_ baudClock.clk $ do nextState :: RxState <- case state of Idle -> do - debug := bit + debugBit := bit if bit == 0 then return (Data 0 0) else return Idle Data hi n -> do - debug := bit - let b = hi[7:1] ++ bit -- <-- weird if i flip + debugBit := bit + -- // Timing estimate: 1000010.53 ns (0.00 MHz) + -- let b :: Bit 8 = bit ++ hi[7:1] + let b :: Bit 8 = hi[7:1] ++ bit if n == 7 then do when_ fifo.notFull $ do fifo.enq b @@ -118,8 +120,13 @@ mkRxUart baudClock bufferSize = else return (Data b (n + 1)) state := nextState - recv = toGet fifo - bit = debug + recv = interface Get + get = do + let byte = fifo.first + fifo.deq + return byte + when fifo.notEmpty + debugBit = debugBit -- | An 8n1 UART. interface Uart = @@ -132,7 +139,7 @@ interface Uart = recv :: Get (Bit 8) -- | Writes a byte to the UART's transmit buffer. send :: Put (Bit 8) - bit :: Bit 1 + debugBit :: Bit 1 mkUart :: Integer -> Module Uart mkUart baudDivisor = @@ -146,6 +153,6 @@ mkUart baudDivisor = txPin = tx.pin recv = rx.recv send = tx.send - bit = rx.bit + debugBit = rx.debugBit -- vim: set ft=haskell : |