1 files changed, 55 insertions, 20 deletions
diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs
index e4e65c9..2a58a83 100644
--- a/fpga/src/TopSim.bs
+++ b/fpga/src/TopSim.bs
@@ -29,28 +29,63 @@ mkTopSim = module
     when True ==> txSCL := i2c.txSCL
     when True ==> txSDA := i2c.txSDA
 
-  timer :: Reg (Bit 16) <- mkReg 0
+  -- Provide commands.
+  state :: Reg (Bit 4) <- mkReg 0
   rules
-    "t0000": when (timer == 0x0000) ==> do
-      i2c.addrReg := 0x20 ++ (0 :: Bit 1)
-      i2c.dataReg := 0x12
-    "t0001": when (timer == 0x0001) ==> do
-      i2c.statusReg := i2c.statusReg { ready = False; dataAckBit = True }
-    "t0002": when (timer == 0x0002) ==> do
-      i2c.addrReg := 0x20 ++ (0 :: Bit 1)
-      i2c.dataReg := 0xaa
-    "t0022": when (timer == 0x0023) ==> rxSDA := 0
-    "t0025": when (timer == 0x0027) ==> rxSDA := 1
-    -- "t0047": when (timer == 0x0047) ==> rxSDA := 0
-    -- "t0051": when (timer == 0x004b) ==> rxSDA := 1
-    -- "t004b": when (timer == 0x004b) ==> do
-      -- i2c.statusReg := i2c.statusReg { ready = False }
-    "advance timer": when True ==> timer := timer + 1
-    "finish": when (timer == 0x00ff) ==> $finish
+    when state == 0, i2c.statusRegGet.ready ==> do
+      i2c.addrRegPut (0x20 ++ (0 :: Bit 1))
+      i2c.dataRegPut 0x01
+      i2c.statusRegPut (i2c.statusRegGet { ready = False })
+      state := 1
+    when state == 1 ==> do
+      i2c.addrRegPut (0x20 ++ (0 :: Bit 1))
+      i2c.dataRegPut 0x02
+      state := 2
+    when state == 2, i2c.statusRegGet.ready ==> do
+      i2c.statusRegPut (i2c.statusRegGet { ready = False })
+      state := 3
     {-
-    "log received values": when True ==> do
-      result <- i2c.recv.get
-      $display "recv: " (fshow result)
+    when state == 3 ==> do
+      i2c.addrRegPut (0x20 ++ (0 :: Bit 1))
+      i2c.dataRegPut 0x03
+      state := 4
+    when state == 4, i2c.statusRegGet.ready ==> do
+      i2c.statusRegPut (i2c.statusRegGet { ready = False })
+      state := 5
+    when state == 5 ==> do
+      i2c.addrRegPut (0x20 ++ (0 :: Bit 1))
+      i2c.dataRegPut 0x12
+      state := 6
+    when state == 6, i2c.statusRegGet.busIdle ==> do
+      i2c.statusRegPut (i2c.statusRegGet { ready = False })
+      state := 7
+    when state == 7 ==> do
+      i2c.addrRegPut (0x20 ++ (0 :: Bit 1))
+      i2c.dataRegPut 0xaa
+      state := 8
+    when state == 8, i2c.statusRegGet.ready ==> do
+      i2c.statusRegPut (i2c.statusRegGet { ready = False })
+      state := 9
+    when state == 9 ==> do
+      i2c.addrRegPut (0x20 ++ (0 :: Bit 1))
+      i2c.dataRegPut 0xaa
+      state := 10
+    when state == 10, i2c.statusRegGet.ready ==> do
+      i2c.statusRegPut (i2c.statusRegGet { ready = False })
+      state := 11
     -}
 
+  timer :: Reg (Bit 16) <- mkReg 0
+  rules
+    "t0022": when (timer == 0x0022) ==> rxSDA := 0
+    "t0026": when (timer == 0x0026) ==> rxSDA := 1
+    "t0046": when (timer == 0x0046) ==> rxSDA := 0
+    "t004a": when (timer == 0x004a) ==> rxSDA := 1
+    "t006a": when (timer == 0x006a) ==> rxSDA := 0
+    "t006e": when (timer == 0x006e) ==> rxSDA := 1
+    "t008e": when (timer == 0x008e) ==> rxSDA := 0
+    "t0092": when (timer == 0x0092) ==> rxSDA := 1
+    "advance timer": when True ==> timer := timer + 1
+    "finish": when (timer == 0x01ff) ==> $finish
+
 -- vim: set ft=haskell :