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-rw-r--r--fpga/src/TopSim.bs32
1 files changed, 0 insertions, 32 deletions
diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs
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index d0d17cb..0000000
--- a/fpga/src/TopSim.bs
+++ /dev/null
@@ -1,32 +0,0 @@
-package TopSim where
-
-import App
-import GetPut
-import Uart
-
-mkTopSim :: Module Empty
-mkTopSim =
- module
- timer :: Reg (Bit 8) <- mkReg 0
-
- uart <- mkUart 1
- app <- mkApp uart.recv uart.send
-
- fakeUart <- mkUart 1
-
- rules
- when True ==> timer := timer + 1
- when True ==> uart.rxPin fakeUart.txPin
- when (timer == 0x00) ==> fakeUart.send.put 0x30
- when (timer == 0x01) ==> fakeUart.send.put 0x30
- when (timer == 0x02) ==> fakeUart.send.put 0x77
- when (timer == 0x03) ==> fakeUart.send.put 0x31
- when (timer == 0x04) ==> fakeUart.send.put 0x32
- when (timer == 0x05) ==> fakeUart.send.put 0x33
- when (timer == 0x06) ==> fakeUart.send.put 0x34
- when (timer == 0x10) ==> fakeUart.send.put 0x30
- when (timer == 0x11) ==> fakeUart.send.put 0x30
- when (timer == 0x12) ==> fakeUart.send.put 0x72
- when (timer == 0xff) ==> $finish
-
--- vim: set ft=haskell :