diff options
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/Makefile | 2 | ||||
| -rw-r--r-- | fpga/src/Top.bs | 30 | ||||
| -rw-r--r-- | fpga/src/TopSim.bs | 38 |
3 files changed, 40 insertions, 30 deletions
diff --git a/fpga/Makefile b/fpga/Makefile index f2fa1f4..d71968c 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -30,6 +30,6 @@ tmp/mkTopSim.exe: tmp/mkTopSim.ba bsc -sim -e mkTopSim $(BSC_LINK_FLAGS) -o $@ tmp/mkTopSim.ba: @mkdir -p $(dir $@) - bsc -u -sim -g mkTopSim $(BSC_COMP_FLAGS) src/Top.bs + bsc -u -sim -g mkTopSim $(BSC_COMP_FLAGS) src/TopSim.bs .PHONY: tmp/mkTop.v tmp/mkTopSim.ba diff --git a/fpga/src/Top.bs b/fpga/src/Top.bs index 7740c4b..29558d4 100644 --- a/fpga/src/Top.bs +++ b/fpga/src/Top.bs @@ -1,4 +1,4 @@ --- | The top-level module, for both simulation and the iCEBreaker. +-- | The top-level module, for the iCEBreaker. package Top where import Connectable @@ -109,32 +109,4 @@ mkTop = {-# verilog mkTop #-} {-# properties mkTop = { RSTN = BTN_N } #-} -mkTopSim :: Module Empty -mkTopSim = - module - cpu <- mkCPU - - uart <- mkUart 1 - mkConnection cpu.uart_tx uart.send - mkConnection cpu.uart_rx uart.recv - - fakeUart <- mkUart 1 - rules - when True ==> uart.rxPin fakeUart.txPin - - timer :: Reg (Bit 8) <- mkReg 0 - rules - when True ==> timer := timer + 1 - when (timer == 0x00) ==> fakeUart.send.put 0x30 - when (timer == 0x01) ==> fakeUart.send.put 0x30 - when (timer == 0x02) ==> fakeUart.send.put 0x77 - when (timer == 0x03) ==> fakeUart.send.put 0x31 - when (timer == 0x04) ==> fakeUart.send.put 0x32 - when (timer == 0x05) ==> fakeUart.send.put 0x33 - when (timer == 0x06) ==> fakeUart.send.put 0x34 - when (timer == 0x10) ==> fakeUart.send.put 0x30 - when (timer == 0x11) ==> fakeUart.send.put 0x30 - when (timer == 0x12) ==> fakeUart.send.put 0x72 - when (timer == 0xff) ==> $finish - -- vim: set ft=haskell : diff --git a/fpga/src/TopSim.bs b/fpga/src/TopSim.bs new file mode 100644 index 0000000..ca92fe1 --- /dev/null +++ b/fpga/src/TopSim.bs @@ -0,0 +1,38 @@ +-- | The top-level module for simulation. +package TopSim where + +import Connectable +import CPU +import GetPut +import TriState +import Uart + +mkTopSim :: Module Empty +mkTopSim = + module + cpu <- mkCPU + + uart <- mkUart 1 + mkConnection cpu.uart_tx uart.send + mkConnection cpu.uart_rx uart.recv + + fakeUart <- mkUart 1 + rules + when True ==> uart.rxPin fakeUart.txPin + + timer :: Reg (Bit 8) <- mkReg 0 + rules + when True ==> timer := timer + 1 + when (timer == 0x00) ==> fakeUart.send.put 0x30 + when (timer == 0x01) ==> fakeUart.send.put 0x30 + when (timer == 0x02) ==> fakeUart.send.put 0x77 + when (timer == 0x03) ==> fakeUart.send.put 0x31 + when (timer == 0x04) ==> fakeUart.send.put 0x32 + when (timer == 0x05) ==> fakeUart.send.put 0x33 + when (timer == 0x06) ==> fakeUart.send.put 0x34 + when (timer == 0x10) ==> fakeUart.send.put 0x30 + when (timer == 0x11) ==> fakeUart.send.put 0x30 + when (timer == 0x12) ==> fakeUart.send.put 0x72 + when (timer == 0xff) ==> $finish + +-- vim: set ft=haskell : |