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| author | Nathan Ringo <nathan@remexre.com> | 2024-05-05 17:20:00 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-05-05 17:20:00 -0500 |
| commit | 0874c7f1852145c3ae62f1e28dc10c0c89d78b45 (patch) | |
| tree | 0717d0293a78510ac62ea7f463da4ef6d54229cb /Makefile | |
| parent | 2ec6d7d09e2cd6c08686aae9427b46a217972675 (diff) | |
Not yet working UART...
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 39 |
1 files changed, 28 insertions, 11 deletions
@@ -1,19 +1,36 @@ -BSC_COMP_FLAGS = -aggressive-conditions -check-assert -keep-fires +BSC_COMP_FLAGS = -aggressive-conditions -bdir tmp -check-assert -keep-fires \ + -p src:$(BSC_CONTRIB)/Libraries/FPGA/Misc:+ -vdir tmp BSC_LINK_FLAGS = -keep-fires +BSC_SOURCES = Counter.v SizedFIFO.v TOPFILE = Top TOPMODULE = mkTop +SRCS = $(shell find src -name '*.bs') -all: tmp/$(TOPMODULE).exe tmp/$(TOPMODULE).v +all: tmp/$(TOPMODULE).bin clean: clean.sh - @./clean.sh -.PHONY: all clean + @git status --porcelain=v1 --ignored -z \ + | grep -z '^!!' \ + | xargs -0 awk 'BEGIN { for(i = 1; i < ARGC; i++) printf "%s%c", substr(ARGV[i], 4), 0; }' \ + | xargs -0 rm -r +flash: tmp/$(TOPMODULE).bin + sudo iceprog $< +.PHONY: all clean flash -tmp/$(TOPMODULE).exe: tmp/$(TOPMODULE).ba +tmp/%.bin: tmp/%.asc + # icetime -d up5k -c 12 $< + icepack $< $@ +tmp/%.asc: tmp/%.json src/icebreaker.pcf + nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \ + --asc $@ --pcf src/icebreaker.pcf --json $< +tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES)) + yosys -ql tmp/$(TOPMODULE).yslog -p 'synth_ice40 -top mkTop -json $@' $^ +tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo + bsc -g $(TOPMODULE) -verilog $(BSC_COMP_FLAGS) src/$(TOPFILE).bs +tmp/%.bo: @mkdir -p $(dir $@) - bsc -e $(TOPMODULE) -o $@ -p $(dir $<) -sim -simdir tmp -u $(BSC_LINK_FLAGS) -tmp/$(TOPMODULE).ba: src/$(TOPFILE).bs - @mkdir -p $(dir $@) - bsc -bdir $(dir $@) -g $(TOPMODULE) -sim -u $(BSC_COMP_FLAGS) $< -tmp/$(TOPMODULE).v: src/$(TOPFILE).bs + bsc -verilog $(BSC_COMP_FLAGS) $< + +tmp/depends.mk: @mkdir -p $(dir $@) - bsc -bdir tmp -g $(TOPMODULE) -u -verilog -vdir tmp $(BSC_COMP_FLAGS) $< + bluetcl -exec makedepend $(BSC_COMP_FLAGS) src/$(TOPFILE).bs > $@ +include tmp/depends.mk |