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| author | Nathan Ringo <nathan@remexre.com> | 2024-10-23 08:24:53 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-23 08:24:53 -0500 |
| commit | 76ce6c75b4bd723aabfd0fd6f4d310d3ed90e7fd (patch) | |
| tree | 07d85a95b8af5eca9e5e43793456522b9d027f96 /fpga/Makefile | |
| parent | 2465e4ba5926f3137bb10f1d17944a56425332a3 (diff) | |
checkpoint; something is broken with timing
Diffstat (limited to 'fpga/Makefile')
| -rw-r--r-- | fpga/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/Makefile b/fpga/Makefile index 8219ab3..ac618b0 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -16,7 +16,7 @@ tmp/%.asc tmp/%-report.json: tmp/%.json src/icebreaker.pcf --asc $@ --report tmp/$*-report.json \ --pcf src/icebreaker.pcf --json $< tmp/mkTop.json: tmp/mkTop.rewritten.v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES)) - yosys -ql tmp/mkTop.yslog -p 'synth_ice40 -top mkTop -json $@' $^ + yosys -ql tmp/mkTop.yslog -p 'synth_ice40 -device u -top mkTop -json $@' $^ tmp/mkTop.rewritten.v: tmp/mkTop.v cp $< $@ perl $(BSC_SRC)/util/scripts/basicinout.pl $@ |