Reorganization and rewiring.

1 files changed, 19 insertions, 0 deletions

diff --git a/fpga/src/Clock.bs b/fpga/src/Clock.bs
new file mode 100644
index 0000000..c908502
--- /dev/null
+++ b/fpga/src/Clock.bs
@@ -0,0 +1,19 @@
+-- | A simple clock package.
+package Clock where
+
+interface Clock =
+  clk :: Bool
+
+-- TODO: Make a multiclock that uses one count for all the sub-clocks in the
+-- design.
+
+mkClock :: Bit n -> Module Clock
+mkClock divisor =
+  module
+    count :: Reg (Bit n) <- mkReg 0
+    rules
+      when True ==> count := if count == divisor - 1 then 0 else count + 1
+    interface Clock
+      clk = count == 0
+
+-- vim: set ft=haskell :