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| author | Nathan Ringo <nathan@remexre.com> | 2024-10-20 17:49:23 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-20 17:49:23 -0500 |
| commit | 5c89c77fcf7493778732c12e2b141b5e9fa1f4a3 (patch) | |
| tree | 943e0a339d28f8ef3a7aa7aaf8ad09f94ba63186 /fpga/src/HyperBus.bs | |
| parent | ddf01d51c3429c25a57077d93d3309ce0e5d2262 (diff) | |
Maybe repaired UART, I2C, and HyperBus (but now getting a weird error)...
Diffstat (limited to 'fpga/src/HyperBus.bs')
| -rw-r--r-- | fpga/src/HyperBus.bs | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/fpga/src/HyperBus.bs b/fpga/src/HyperBus.bs index 2b75b6e..b841a64 100644 --- a/fpga/src/HyperBus.bs +++ b/fpga/src/HyperBus.bs @@ -13,7 +13,7 @@ interface HyperBusOut = rwds_out :: Maybe (Bit 1) dq_out :: Maybe (Bit 8) -mkHyperBus :: Wire (Bit 1) -> Wire (Bit 8) -> Module HyperBusOut +mkHyperBus :: Bit 1 -> Bit 8 -> Module HyperBusOut mkHyperBus rwds_in dq_in = module clockPin :: Reg (Bit 1) <- mkReg 0 rules @@ -31,4 +31,9 @@ mkHyperBus rwds_in dq_in = module rwds_out = Nothing dq_out = Nothing +mkDividedHyperBus :: Integer -> Bit 1 -> Bit 8 -> Module HyperBusOut +mkDividedHyperBus _divisor rwds_in dq_in = module + -- TODO + mkHyperBus rwds_in dq_in + -- vim: set ft=haskell : |