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| author | Nathan Ringo <nathan@remexre.com> | 2024-10-08 21:33:12 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-08 21:33:12 -0500 |
| commit | ddf01d51c3429c25a57077d93d3309ce0e5d2262 (patch) | |
| tree | ba8fa87bd190adfd02ff54092dbb57791bb7218e /fpga/src/HyperBus.bs | |
| parent | 08d727e9886cde6a367906999e96a33f7ba37f33 (diff) | |
Preparation to start using separate clock domains.
Diffstat (limited to 'fpga/src/HyperBus.bs')
| -rw-r--r-- | fpga/src/HyperBus.bs | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/fpga/src/HyperBus.bs b/fpga/src/HyperBus.bs index 41d1703..2b75b6e 100644 --- a/fpga/src/HyperBus.bs +++ b/fpga/src/HyperBus.bs @@ -1,8 +1,6 @@ -- | A controller for a HyperBus interface, allowing for I/O to four chips. package HyperBus where -import Clock - -- | The HyperBus output pins. interface HyperBusOut = ck :: Bit 1 @@ -15,11 +13,16 @@ interface HyperBusOut = rwds_out :: Maybe (Bit 1) dq_out :: Maybe (Bit 8) -mkHyperBus :: Wire (Bit 1) -> Wire (Bit 8) -> Clock -> Module HyperBusOut -mkHyperBus rwds_in dq_in clock = module +mkHyperBus :: Wire (Bit 1) -> Wire (Bit 8) -> Module HyperBusOut +mkHyperBus rwds_in dq_in = module + clockPin :: Reg (Bit 1) <- mkReg 0 + rules + "update_clock_pin": when True ==> do + clockPin := invert clockPin + interface HyperBusOut - ck = if clock.clk then 1 else 0 - ck_n = if clock.clk then 0 else 1 + ck = clockPin + ck_n = invert clockPin cs0_n = 1 cs1_n = 1 cs2_n = 1 |