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| author | Nathan Ringo <nathan@remexre.com> | 2024-10-08 21:33:12 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-10-08 21:33:12 -0500 |
| commit | ddf01d51c3429c25a57077d93d3309ce0e5d2262 (patch) | |
| tree | ba8fa87bd190adfd02ff54092dbb57791bb7218e /fpga/src/Top.bs | |
| parent | 08d727e9886cde6a367906999e96a33f7ba37f33 (diff) | |
Preparation to start using separate clock domains.
Diffstat (limited to 'fpga/src/Top.bs')
| -rw-r--r-- | fpga/src/Top.bs | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/fpga/src/Top.bs b/fpga/src/Top.bs index df79387..67449bd 100644 --- a/fpga/src/Top.bs +++ b/fpga/src/Top.bs @@ -1,12 +1,8 @@ -- | The top-level module, for the iCEBreaker. package Top where -import Connectable -import CPU -import GetPut import Numini import TriState -import Uart -- | The interface to the iCEBreaker. interface Top = |