Preparation to start using separate clock domains.

1 files changed, 45 insertions, 57 deletions

diff --git a/fpga/src/Uart.bs b/fpga/src/Uart.bs
index 7298083..82f8e06 100644
--- a/fpga/src/Uart.bs
+++ b/fpga/src/Uart.bs
@@ -1,6 +1,5 @@
 package Uart where
 
-import Clock
 import FIFOF
 import GetPut
 
@@ -26,34 +25,32 @@ interface TxUart =
   -- | Writes a byte to the UART's transmit buffer.
   send :: Put (Bit 8)
 
-mkTxUart :: Clock -> Integer -> Module TxUart
-mkTxUart clock bufferSize =
-  module
-    fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize
-    state :: Reg TxState <- mkReg Idle
-    pin :: Reg (Bit 1) <- mkReg 1
+mkTxUart :: Integer -> Module TxUart
+mkTxUart bufferSize = module
+  fifo :: FIFOF (Bit 8) <- mkSizedFIFOF bufferSize
+  state :: Reg TxState <- mkReg Idle
+  pin :: Reg (Bit 1) <- mkReg 1
 
-    rules
-      "uart_tx": when clock.clk
-        rules
-          "uart_tx_idle": when Idle <- state, not fifo.notEmpty ==> do
-            pin := 1
-          "uart_tx_idle_to_start": when Idle <- state, fifo.notEmpty ==> do
-            pin := 1
-            b <- (toGet fifo).get
-            state := Start b
-          "uart_tx_start": when Start b <- state ==> do
-            pin := 0
-            state := Data b 7
-          "uart_tx_data": when Data b n <- state ==> do
-            pin := b[0:0]
-            if n == 0 then
-              state := Idle
-            else
-              state := Data (b >> 1) (n - 1)
-    interface TxUart
-      pin = pin
-      send = toPut fifo
+  rules
+    "uart_tx_idle": when Idle <- state, not fifo.notEmpty ==> do
+      pin := 1
+    "uart_tx_idle_to_start": when Idle <- state, fifo.notEmpty ==> do
+      pin := 1
+      b <- (toGet fifo).get
+      state := Start b
+    "uart_tx_start": when Start b <- state ==> do
+      pin := 0
+      state := Data b 7
+    "uart_tx_data": when Data b n <- state ==> do
+      pin := b[0:0]
+      if n == 0 then
+        state := Idle
+      else
+        state := Data (b >> 1) (n - 1)
+
+  interface TxUart
+    pin = pin
+    send = toPut fifo
 
 -- | The state of the RX side of the UART.
 data RxState
@@ -71,32 +68,23 @@ data RxState
     Stop (Bit 8)
   deriving (Bits, FShow)
 
--- | The RX side of the UART.
-interface RxUart =
-  -- | Reads a byte from the UART's receive buffer.
-  recv :: Get (Bit 8)
-
-mkRxUart :: Wire (Bit 1) -> Clock -> Integer -> Module RxUart
-mkRxUart rx clock bufferSize =
-  module
-    fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize
-    state :: Reg RxState <- mkReg Idle
+mkRxUart :: Wire (Bit 1) -> Integer -> Module (Get (Bit 8))
+mkRxUart rx bufferSize = module
+  fifo :: FIFOF (Bit 8) <- mkGSizedFIFOF True False bufferSize
+  state :: Reg RxState <- mkReg Idle
 
-    rules
-      "uart_rx": when clock.clk
-        rules
-          "uart_rx_idle_to_start": when Idle <- state, rx == 0 ==> do
-            state := Data 0 0
-          "uart_rx_data_to_data": when Data bits n <- state, n < 7 ==> do
-            state := Data (rx ++ bits[7:1]) (n + 1)
-          "uart_rx_data_to_stop": when Data bits 7 <- state ==> do
-            state := Stop (rx ++ bits[7:1])
-          "uart_rx_stop_to_idle": when Stop bits <- state, rx == 1 ==> do
-            fifo.enq bits
-            state := Idle
+  rules
+    "uart_rx_idle_to_start": when Idle <- state, rx == 0 ==> do
+      state := Data 0 0
+    "uart_rx_data_to_data": when Data bits n <- state, n < 7 ==> do
+      state := Data (rx ++ bits[7:1]) (n + 1)
+    "uart_rx_data_to_stop": when Data bits 7 <- state ==> do
+      state := Stop (rx ++ bits[7:1])
+    "uart_rx_stop_to_idle": when Stop bits <- state, rx == 1 ==> do
+      fifo.enq bits
+      state := Idle
 
-    interface RxUart
-      recv = toGet fifo
+  return (toGet fifo)
 
 -- | An 8n1 UART.
 interface Uart =
@@ -108,13 +96,13 @@ interface Uart =
   -- | Writes a byte to the UART's transmit buffer.
   send :: Put (Bit 8)
 
-mkUart :: Wire (Bit 1) -> Clock -> Module Uart
-mkUart rx clock = module
-  uart_rx <- mkRxUart rx clock 8
-  uart_tx <- mkTxUart clock 8
+mkUart :: Wire (Bit 1) -> Module Uart
+mkUart rx = module
+  recv <- mkRxUart rx 8
+  uart_tx <- mkTxUart 8
   interface Uart
     tx = uart_tx.pin
-    recv = uart_rx.recv
+    recv = recv
     send = uart_tx.send
 
 -- vim: set ft=haskell :