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| author | Nathan Ringo <nathan@remexre.com> | 2024-09-18 14:09:34 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-09-18 14:09:34 -0500 |
| commit | d202daead0f05ecb60580fa7be2f23df8c4542fc (patch) | |
| tree | 027a67c9245bb21bc82c7e52dfd7d989f4900821 /src/TopSim.bs | |
| parent | 46457cc330049bb38c0af9a3f671b33b8f534c55 (diff) | |
Fix the UART TX.
Diffstat (limited to 'src/TopSim.bs')
| -rw-r--r-- | src/TopSim.bs | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/TopSim.bs b/src/TopSim.bs index 5ba7232..93fef14 100644 --- a/src/TopSim.bs +++ b/src/TopSim.bs @@ -1,16 +1,23 @@ package TopSim where +import GetPut import Top +import Uart mkTopSim :: Module Empty mkTopSim = module timer :: Reg (Bit 8) <- mkReg 0 + uart <- mkUart 1 + rules when True ==> do timer := timer + 1 - when (timer == 0xff) ==> do + when (timer == 0x00) ==> uart.send.put 0x81 + when (timer == 0x01) ==> uart.send.put 0x18 + when (timer == 0x02) ==> uart.send.put 0x81 + when (timer == 0x40) ==> do $finish -- vim: set ft=haskell : |