Add the simulator.

2 files changed, 26 insertions, 4 deletions

diff --git a/src/TopSim.bs b/src/TopSim.bs
new file mode 100644
index 0000000..5ba7232
--- /dev/null
+++ b/src/TopSim.bs
@@ -0,0 +1,16 @@
+package TopSim where
+
+import Top
+
+mkTopSim :: Module Empty
+mkTopSim =
+  module
+    timer :: Reg (Bit 8) <- mkReg 0
+
+    rules
+      when True ==> do
+        timer := timer + 1
+      when (timer == 0xff) ==> do
+        $finish
+
+-- vim: set ft=haskell :
diff --git a/src/Uart.bs b/src/Uart.bs
index adf77d4..f66970c 100644
--- a/src/Uart.bs
+++ b/src/Uart.bs
@@ -83,8 +83,12 @@ data RxState
   | -- | In the 'Data _ n' state, the UART has received the start bit and 'n'
     -- data bits, and is about to receive more data bits. 'Data _ n'
     -- transitions to 'Data _ (n + 1)' by receiving a data bit. 'Data b 7'
-    -- transitions to 'Idle' by receving the last data bit.
+    -- transitions to 'Stop' by receving the last data bit.
     Data (Bit 8) (Bit 3)
+  | -- | In the 'Stop' state, the UART has received the start and data bits,
+    -- and is waiting for the stop bit (which is ignored). Transitions to
+    -- 'Idle'.
+    Stop
   deriving (Bits)
 
 -- | The RX side of the UART.
@@ -109,7 +113,7 @@ mkRxUart baudClock bufferSize =
         rules
           "uart_rx_idle": when Idle <- state ==>
             if pin == 0 then do
-              debugBit := 0
+              debugBit := pin
               state := Data 0 0
             else
               state := Idle
@@ -117,10 +121,12 @@ mkRxUart baudClock bufferSize =
             let newBits = pin ++ oldBits[6:0]
             if n == 7 then do
               fifo.enq newBits
-              debugBit := 1
-              state := Idle
+              state := Stop
             else
               state := Data newBits (n + 1)
+          "uart_rx_stop": when Stop <- state ==> do
+            debugBit := pin
+            state := Idle
 
     interface RxUart
       pin bit = pin := bit