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| author | Nathan Ringo <nathan@remexre.com> | 2024-05-06 01:12:26 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-05-06 01:12:26 -0500 |
| commit | d8db4d5cfa3977001181714e632d5addd7c0e4ba (patch) | |
| tree | e01d034e671c0039864850fbeca319593b2468f6 /Makefile | |
| parent | f9b73dc7b93bbf60f5b2281a5056c4339e049388 (diff) | |
Sending side done!
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -1,6 +1,7 @@ BSC_COMP_FLAGS = -aggressive-conditions -bdir tmp -check-assert -keep-fires \ -p src:+ -vdir tmp BSC_LINK_FLAGS = -keep-fires +BSC_SOURCES = FIFO1.v TOPFILE = Top TOPMODULE = mkTop SRCS = $(shell find src -name '*.bs') @@ -21,7 +22,7 @@ tmp/%.bin: tmp/%.asc tmp/%.asc: tmp/%.json src/icebreaker.pcf nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \ --asc $@ --pcf src/icebreaker.pcf --json $< -tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v +tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES)) yosys -ql tmp/$(TOPMODULE).yslog -p 'synth_ice40 -top mkTop -json $@' $^ tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo bsc -g $(TOPMODULE) -verilog $(BSC_COMP_FLAGS) src/$(TOPFILE).bs |