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| author | Nathan Ringo <nathan@remexre.com> | 2024-05-05 22:30:50 -0500 |
|---|---|---|
| committer | Nathan Ringo <nathan@remexre.com> | 2024-05-05 22:30:50 -0500 |
| commit | f9b73dc7b93bbf60f5b2281a5056c4339e049388 (patch) | |
| tree | 5325a2e6ee78bb36179c5b2b4c56da806214e426 /Makefile | |
| parent | 0874c7f1852145c3ae62f1e28dc10c0c89d78b45 (diff) | |
triyng a uart from scratch... not yet working...
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 9 |
1 files changed, 4 insertions, 5 deletions
@@ -1,13 +1,12 @@ BSC_COMP_FLAGS = -aggressive-conditions -bdir tmp -check-assert -keep-fires \ - -p src:$(BSC_CONTRIB)/Libraries/FPGA/Misc:+ -vdir tmp + -p src:+ -vdir tmp BSC_LINK_FLAGS = -keep-fires -BSC_SOURCES = Counter.v SizedFIFO.v TOPFILE = Top TOPMODULE = mkTop SRCS = $(shell find src -name '*.bs') all: tmp/$(TOPMODULE).bin -clean: clean.sh +clean: @git status --porcelain=v1 --ignored -z \ | grep -z '^!!' \ | xargs -0 awk 'BEGIN { for(i = 1; i < ARGC; i++) printf "%s%c", substr(ARGV[i], 4), 0; }' \ @@ -17,12 +16,12 @@ flash: tmp/$(TOPMODULE).bin .PHONY: all clean flash tmp/%.bin: tmp/%.asc - # icetime -d up5k -c 12 $< + icetime -d up5k -c 12 $< icepack $< $@ tmp/%.asc: tmp/%.json src/icebreaker.pcf nextpnr-ice40 -ql tmp/$*.nplog --up5k --package sg48 --freq 12 \ --asc $@ --pcf src/icebreaker.pcf --json $< -tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v $(addprefix $(BSC)/lib/Verilog/,$(BSC_SOURCES)) +tmp/$(TOPMODULE).json: tmp/$(TOPMODULE).v yosys -ql tmp/$(TOPMODULE).yslog -p 'synth_ice40 -top mkTop -json $@' $^ tmp/$(TOPMODULE).v: tmp/$(TOPFILE).bo bsc -g $(TOPMODULE) -verilog $(BSC_COMP_FLAGS) src/$(TOPFILE).bs |